Datasheet TDA4662T-V3, TDA4662T-V1, TDA4662T-V2, TDA4662-V3, TDA4662-V2 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1995 Oct 30
File under Integrated Circuits, IC02

1996 Nov 14

INTEGRATED CIRCUITS

TDA4662

Baseband delay line

1996 Nov 14 2

Philips Semiconductors Product specification

Baseband delay line TDA4662

FEATURES

• Two comb filters, using the switched-capacitor
technique, for one line delay time (64 µs)

• For PAL and NTSC

• Adjustment-free application

• Handles negative or positive colour-difference input

signals

• Clamping of AC-coupled input signals [±(R−Y) and
±(B−Y)]

• VCO without external components

• 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 µs line)

• Sample-and-hold circuits and low-pass filters to

suppress the 3 MHz clock signal

• Addition of delayed and non-delayed output signals

• Output buffer amplifiers

• Comb filtering functions for NTSC colour-difference

signals to suppress cross-colour.

GENERAL DESCRIPTION

The TDA4662 is an integrated baseband delay line circuit
with one line delay. It is suitable for PAL and NTSC
decoders with colour-difference signal outputs±(R−Y) and
±(B−Y).

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

P1

analog supply voltage (pin 9) 4.5 5 6 V

V

P2

digital supply voltage (pin 1) 4.5 5 6 V

I

P(tot)

total supply current − 5.5 7.0 mA

V

i(p-p)

±(R−Y) input signal PAL/NTSC (peak-to-peak value; pin 16) − 525 − mV
±(B−Y) input signal PAL/NTSC (peak-to-peak value; pin 14) − 665 − mV

G

v

voltage gain VO/VI of colour-difference output signals

V

11/V16

for PAL and NTSC 5.3 5.8 6.3 dB

V

12/V14

for PAL and NTSC 5.3 5.8 6.3 dB

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA4662 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
TDA4662T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

1996 Nov 14 3

Philips Semiconductors Product specification

Baseband delay line TDA4662

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

SANDCASTLE

DETECTOR

FREQUENCY

PHASE

DETECTOR

DIVIDE-

BY-192

LP

V

P2

3 MHz shifting clock

1

digital supply

LINE

MEMORY

SIGNAL

CLAMPING

SAMPLE-

AND-HOLD

6 MHz

CCO

DIVIDE-

BY-2

LP

addition

stages

output

buffers

colour-difference

output signals

colour-difference

input signals

12

2

5

10

GND1

3

n.c.

6

n.c.13n.c.15n.c.7i.c.

4, 8

±(B−Y)

±(R−Y)

±(R−Y)

±(B−Y)

V

P1

sandcastle

input

GND2

9

14

LINE

MEMORY

TDA4662

SIGNAL

CLAMPING

pre-amplifiers

SAMPLE-

AND-HOLD

LP

11

16

analog supply

MED743

1996 Nov 14 4

Philips Semiconductors Product specification

Baseband delay line TDA4662

PINNING

SYMBOL PIN DESCRIPTION

V

P2

1 supply voltage for digital part (+5 V)
n.c. 2 not connected
GND2 3 ground for digital part (0 V)
i.c. 4 internally connected
SAND 5 sandcastle pulse input
n.c. 6 not connected
i.c. 7 internally connected
i.c. 8 internally connected
V

P1

9 supply voltage for analog part (+5 V)
GND1 10 ground for analog part (0 V)
V

o(R−Y)

11 ±(R−Y) output signal

V

o(B−Y)

12 ±(B−Y) output signal
n.c. 13 not connected
V

i(B−Y)

14 ±(B−Y) input signal
n.c. 15 not connected
V

i(R−Y)

16 ±(R−Y) input signal

Fig.2 Pin configuration.

handbook, halfpage

TDA4662

MED744

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

P2

n.c.

GND2

i.c.

SAND

n.c.

i.c.
i.c.

V

P1

GND1

V

o(R−Y)

V

o(B−Y)

n.c.

V

i(B−Y)

n.c.

V

i(R−Y)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together.

Note

1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P1

supply voltage (pin 9) −0.5 +7 V

V

P2

supply voltage (pin 1) −0.5 +7 V

V

5

input voltage on pin 5 −0.5 VP+ 1.0 V

V

n

voltage on pins 11, 12, 14 and 16 −0.5 V

P

V

T

stg

storage temperature −25 +150 °C

T

amb

operating ambient temperature 0 70 °C

V

ESD

electrostatic handling for all pins note 1 −±500 V

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

SOT38-4 75 K/W
SOT109-1 220 K/W

1996 Nov 14 5

Philips Semiconductors Product specification

Baseband delay line TDA4662

CHARACTERISTICS

VP= 5 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz;
T

amb

=25°C; measurements taken in Fig.3; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P1

analog supply voltage (pin 9) 4.5 5 6 V

V

P2

digital supply voltage (pin 1) 4.5 5 6 V

I

P1

analog supply current (pin 9) − 4.8 6.0 mA

I

P2

digital supply current (pin 1) − 0.7 1.0 mA

Colour-difference input signals

V

i(p-p)

input signal (peak-to-peak value)

±(R−Y) PAL and NTSC (pin 16) − 525 − mV
±(B−Y) PAL and NTSC (pin 14) − 665 − mV

V

i(max; p-p)

maximum symmetrical input signal
(peak-to-peak value)

±(R−Y) for PAL and NTSC before clipping 660 −−mV
±(B−Y) for PAL and NTSC before clipping 840 −−mV

R

14,16

input resistance during clamping −−40 kΩ

C

14,16

input capacitance −−10 pF

V

14,16

input clamping voltage proportional to V

P

1.3 1.5 1.7 V

Colour-difference output signals

V

o(p-p)

output signal (peak-to-peak value)

±(R−Y) on pin 11 − 1.05 − V
±(B−Y) on pin 12 − 1.33 − V

V

11/V12

ratio of output amplitudes at equal input
signals

V

i14,16

= 665 mV (p-p) −0.4 0 +0.4 dB

V

11,12

DC output voltage proportional to V

P

2.5 2.9 3.3 V

R

11,12

output resistance − 330 400 Ω

G

v

gain for PAL and NTSC ratio Vo/V

i

5.3 5.8 6.3 dB

V

N(rms)

noise voltage
(RMS value; pins 11 and 12)

V

i14,16

= 0 V; note 1 −−1.2 mV

V

11,12(p-p)

unwanted signals (line-locked)
(peak-to-peak value)

V

i14,16

= 0 V; active

video; RS= 300 Ω
meander −−5mV
spikes −−10 mV

S/N(W) weighted signal-to-noise ratio

(pins 11 and 12)

V

o

= 1 V (p-p); note 1 − 54 − dB

t

d

time difference between undelayed and
delayed output signals (pins 11and 12)

63.94 64 64.06 µs

delay of undelayed signals 40 60 80 ns

1996 Nov 14 6

Philips Semiconductors Product specification

Baseband delay line TDA4662

Notes

1. Noise voltage at f = 10 kHz to 1 MHz; RS< 300 Ω.

2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing.

APPLICATION INFORMATION

Sandcastle pulse input (pin 5)

f

BK

burst-key frequency/sandcastle frequency 14.2 15.625 17.0 kHz

V

5

top pulse voltage note 2 4.0 − VP+ 1.0 V

V

slice

internal slicing level V5− 1.0 − V5− 0.5 V

I

5

input current −−10 µA

C

5

input capacitance −−10 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fig.3 Application circuit.

(1) Positioned close to pins.

handbook, full pagewidth

MED745

22 µF

100

nF

100

nF

10 Ω

10 Ω

560 Ω

LINE-LOCKED PLL /

PULSE PROCESSING

VCO

LINE DELAY

LINE DELAY

±(R−Y) comb filtering

±(B−Y) comb filtering

5.1 V

+12 V

16

14

5

10

9

1

3

11

12

V

o(R−Y)

V

o(B−Y)

4
8
7

2
6

13

15

i.c.
n.c.

n.c.
n.c.
n.c.

+5.1 V +5.1 V

TDA4662

(1) (1)

colour

difference

output

signals

colour

difference

input

signals

sandcastle

input

(+5 V)

1 nF
1 nF

V

i(R−Y)

V

i(B−Y)

1996 Nov 14 7

Philips Semiconductors Product specification

Baseband delay line TDA4662

PACKAGE OUTLINES

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT38-4

92-11-17
95-01-14

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

b

2

e

D

A

2

Z

16

1

9

8

E

pin 1 index

b

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

UNIT

A

max.

12

b

1

(1) (1)

(1)

b

2

cD E e M

Z

H

L

mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

min.

A

max.

b

max.

w

M

E

e

1

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

0.764.2 0.51 3.2

inches

0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12

0.010.10 0.30

0.32

0.31

0.39

0.33

0.0300.17 0.020 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

1996 Nov 14 8

Philips Semiconductors Product specification

Baseband delay line TDA4662

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

8

9

1

16

y

pin 1 index

UNIT

A

max.

A1A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

1.27

6.2

5.8

 0.7

0.6

0.7

0.3

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.0

0.4

SOT109-1

91-08-13
95-01-23

076E07S MS-012AC

0.069

0.0098

0.0039

0.057

0.049

0.01

0.019

0.014

0.0098

0.0075

0.39

0.38

0.16

0.15

0.050

1.05

0.041

0.24

0.23

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

1996 Nov 14 9

Philips Semiconductors Product specification

Baseband delay line TDA4662

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

DIP

S

OLDERING BY DIPPING OR BY WA VE

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.
Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

W

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Nov 14 10

Philips Semiconductors Product specification

Baseband delay line TDA4662

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1996 Nov 14 11

Philips Semiconductors Product specification

Baseband delay line TDA4662

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 537021/1200/03/pp12 Date of release: 1996 Nov 14 Document order number: 9397 750 01156