Datasheet TDA4662T, TDA4662 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA4662

Baseband delay line

Product specification
Supersedes data of 1995 Oct 30
File under Integrated Circuits, IC02

1996 Nov 14

Philips Semiconductors Product specification

Baseband delay line TDA4662

FEATURES

• Two comb filters, using the switched-capacitor
technique, for one line delay time (64 µs)

• For PAL and NTSC

• Adjustment-free application

GENERAL DESCRIPTION

The TDA4662 is an integrated baseband delay line circuit
with one line delay. It is suitable for PAL and NTSC
decoders with colour-difference signal outputs±(R−Y) and

±(B−Y).

• Handles negative or positive colour-difference input

signals

• Clamping of AC-coupled input signals [±(R−Y) and
±(B−Y)]

• VCO without external components

• 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 µs line)

• Sample-and-hold circuits and low-pass filters to

suppress the 3 MHz clock signal

• Addition of delayed and non-delayed output signals

• Output buffer amplifiers

• Comb filtering functions for NTSC colour-difference

signals to suppress cross-colour.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

P1

V

P2

I

P(tot)

V

i(p-p)

analog supply voltage (pin 9) 4.5 5 6 V
digital supply voltage (pin 1) 4.5 5 6 V
total supply current − 5.5 7.0 mA

±(R−Y) input signal PAL/NTSC (peak-to-peak value; pin 16) − 525 − mV
±(B−Y) input signal PAL/NTSC (peak-to-peak value; pin 14) − 665 − mV

G

v

voltage gain VO/VI of colour-difference output signals

V
V

for PAL and NTSC 5.3 5.8 6.3 dB

11/V16

for PAL and NTSC 5.3 5.8 6.3 dB

12/V14

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA4662 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
TDA4662T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

1996 Nov 14 2

Philips Semiconductors Product specification

Baseband delay line TDA4662

BLOCK DIAGRAM

±(R−Y)

11

LP

SAMPLE-

AND-HOLD

LINE

MEMORY

output signals

colour-difference

12

output

buffers

stages

addition

pre-amplifiers

±(B−Y)

2

LP

SAMPLE-

AND-HOLD

LINE

MEMORY

n.c.

n.c.13n.c.15n.c.7i.c.

6

TDA4662

3 MHz shifting clock

BY-192

DIVIDE-

PHASE

DETECTOR

FREQUENCY

BY-2

DIVIDE-

CCO

6 MHz

LP

MED743

4, 8
3

GND2

1

P2

V

digital supply

Fig.1 Block diagram.

SIGNAL

CLAMPING

16

±(R−Y)

handbook, full pagewidth

colour-difference

SIGNAL

14

±(B−Y)

input signals

1996 Nov 14 3

CLAMPING

analog supply

9

P1

V

DETECTOR

SANDCASTLE

5

input

sandcastle

10

GND1

Philips Semiconductors Product specification

Baseband delay line TDA4662

PINNING

SYMBOL PIN DESCRIPTION

V

P2

n.c. 2 not connected
GND2 3 ground for digital part (0 V)
i.c. 4 internally connected
SAND 5 sandcastle pulse input
n.c. 6 not connected
i.c. 7 internally connected
i.c. 8 internally connected
V

P1

GND1 10 ground for analog part (0 V)
V

o(R−Y)

V

o(B−Y)

n.c. 13 not connected
V

i(B−Y)

n.c. 15 not connected
V

i(R−Y)

1 supply voltage for digital part (+5 V)

9 supply voltage for analog part (+5 V)

11 ±(R−Y) output signal
12 ±(B−Y) output signal

14 ±(B−Y) input signal

16 ±(R−Y) input signal

handbook, halfpage

V

1

P2

n.c.

2
3

GND2

4

i.c.

SAND

n.c.

i.c.
i.c.

5
6
7
8

TDA4662

MED744

Fig.2 Pin configuration.

16

V

i(R−Y)

15

n.c.

14

V

i(B−Y)

13

n.c.

12

V

o(B−Y)

11

V

o(R−Y)

10

GND1

9

V

P1

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
V
T
T
V

P1
P2
5
n
stg
amb
ESD

supply voltage (pin 9) −0.5 +7 V
supply voltage (pin 1) −0.5 +7 V
input voltage on pin 5 −0.5 VP+ 1.0 V
voltage on pins 11, 12, 14 and 16 −0.5 V

P

V
storage temperature −25 +150 °C
operating ambient temperature 0 70 °C
electrostatic handling for all pins note 1 −±500 V

Note

1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

SOT38-4 75 K/W
SOT109-1 220 K/W

1996 Nov 14 4

Philips Semiconductors Product specification

Baseband delay line TDA4662

CHARACTERISTICS

VP= 5 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz;
T

=25°C; measurements taken in Fig.3; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P1

V

P2

I

P1

I

P2

Colour-difference input signals

V

i(p-p)

V

i(max; p-p)

R

14,16

C

14,16

V

14,16

Colour-difference output signals

V

o(p-p)

V

11/V12

V

11,12

R

11,12

G

v

V

N(rms)

V

11,12(p-p)

S/N(W) weighted signal-to-noise ratio

t

d

analog supply voltage (pin 9) 4.5 5 6 V
digital supply voltage (pin 1) 4.5 5 6 V
analog supply current (pin 9) − 4.8 6.0 mA
digital supply current (pin 1) − 0.7 1.0 mA

input signal (peak-to-peak value)

±(R−Y) PAL and NTSC (pin 16) − 525 − mV
±(B−Y) PAL and NTSC (pin 14) − 665 − mV

maximum symmetrical input signal
(peak-to-peak value)

±(R−Y) for PAL and NTSC before clipping 660 −−mV
±(B−Y) for PAL and NTSC before clipping 840 −−mV

input resistance during clamping −−40 kΩ
input capacitance −−10 pF
input clamping voltage proportional to V

P

1.3 1.5 1.7 V

output signal (peak-to-peak value)

±(R−Y) on pin 11 − 1.05 − V
±(B−Y) on pin 12 − 1.33 − V

ratio of output amplitudes at equal input

V

= 665 mV (p-p) −0.4 0 +0.4 dB

i14,16

signals
DC output voltage proportional to V

P

2.5 2.9 3.3 V
output resistance − 330 400 Ω
gain for PAL and NTSC ratio Vo/V
noise voltage

V

= 0 V; note 1 −−1.2 mV

i14,16

i

5.3 5.8 6.3 dB

(RMS value; pins 11 and 12)
unwanted signals (line-locked)

(peak-to-peak value)

V

= 0 V; active

i14,16

video; RS= 300 Ω
meander −−5mV
spikes −−10 mV

= 1 V (p-p); note 1 − 54 − dB

V

o

(pins 11 and 12)
time difference between undelayed and

63.94 64 64.06 µs

delayed output signals (pins 11and 12)
delay of undelayed signals 40 60 80 ns

1996 Nov 14 5

Philips Semiconductors Product specification

Baseband delay line TDA4662

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Sandcastle pulse input (pin 5)

f

BK

V

5

V

slice

I

5

C

5

Notes

1. Noise voltage at f = 10 kHz to 1 MHz; RS< 300 Ω.

2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing.

APPLICATION INFORMATION

burst-key frequency/sandcastle frequency 14.2 15.625 17.0 kHz
top pulse voltage note 2 4.0 − VP+ 1.0 V
internal slicing level V5− 1.0 − V5− 0.5 V
input current −−10 µA
input capacitance −−10 pF

handbook, full pagewidth

colour

difference

input

signals

sandcastle

input

(+5 V)

V

1 nF
1 nF

V

i(R−Y)

i(B−Y)

TDA4662

±(R−Y) comb filtering

16

LINE DELAY

14

LINE DELAY

±(B−Y) comb filtering

5

LINE-LOCKED PLL /

PULSE PROCESSING

+5.1 V +5.1 V

9

10

(1) (1)

100

nF

22 µF

VCO

10 Ω

10 Ω

V

o(R−Y)

11

V

o(B−Y)

12

4
8

i.c.

7

n.c.

2

n.c.

6

n.c.

13

n.c.

15

1

3

100

nF

560 Ω

+12 V

5.1 V

MED745

colour

difference

output

signals

(1) Positioned close to pins.

Fig.3 Application circuit.

1996 Nov 14 6

Philips Semiconductors Product specification

Baseband delay line TDA4662

PACKAGE OUTLINES

DIP16: plastic dual in-line package; 16 leads (300 mil)

D

seating plane

L

Z

16

pin 1 index

e

b

SOT38-4

M

E

A

2

A

A

1

w M

b

1

b

2

9

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

max.

mm

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT38-4

12

min.

max.

IEC JEDEC EIAJ

b

1.73

1.30

0.068

0.051

b

1

0.53

0.38

0.021

0.015

b

cD E e M

2

0.36

1.25

0.23

0.85

0.014

0.049

0.009

0.033

REFERENCES

19.50

18.55

0.77

0.73

1996 Nov 14 7

8

(1) (1)

6.48

6.20

0.26

0.24

L

e

1

M

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

E

10.0

0.39

0.33

H

8.3

w

max.

0.2542.54 7.62

0.764.2 0.51 3.2

0.010.10 0.30

0.0300.17 0.020 0.13

ISSUE DATE

92-11-17
95-01-14

(1)

Z

Philips Semiconductors Product specification

Baseband delay line TDA4662

SO16: plastic small outline package; 16 leads; body width 3.9 mm

D

c

y

Z

16

pin 1 index

1

e

9

8

w M

b

p

SOT109-1

E

H

E

A

2

A

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT109-1

A

max.

1.75

0.069

A1A2A

0.25

1.45

0.10

1.25

0.0098

0.057

0.0039

0.049

IEC JEDEC EIAJ

076E07S MS-012AC

0.25

0.01

b

3

p

0.49

0.25

0.36

0.19

0.0098

0.019

0.0075

0.014

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

10.0

4.0

9.8

3.8

0.39

0.16

0.15

0.050

0.38

REFERENCES

1996 Nov 14 8

eHELLpQZywv θ

1.27

6.2

5.8

0.24

0.23

1.0

 0.7

1.05

0.4

0.039

0.041

0.016

0.25

0.6

0.028

0.01 0.004

0.020

EUROPEAN

PROJECTION

0.25 0.1

0.01

0.7

0.3

0.028

0.012

ISSUE DATE

91-08-13
95-01-23

o

8

o

0

Philips Semiconductors Product specification

Baseband delay line TDA4662

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

DIP

OLDERING BY DIPPING OR BY WA VE

S
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

R
Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

R
Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

1996 Nov 14 9

Philips Semiconductors Product specification

Baseband delay line TDA4662

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Nov 14 10

Philips Semiconductors Product specification

Baseband delay line TDA4662

NOTES

1996 Nov 14 11

Philips Semiconductors – a worldwide company

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Middle East: see Italy

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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
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© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 537021/1200/03/pp12 Date of release: 1996 Nov 14 Document order number: 9397 750 01156