Datasheet tda1541 DATASHEETS (Philips)

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INTEGRATED CIRCUITS
DATA SH EET
TDA1541
Dual 16-bit DAC
Product specification File under Integrated Circuits, IC01
November 1985
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Dual 16-bit DAC TDA1541

GENERAL DESCRIPTION

The TDA1541 is a monolithic integrated dual 16-bit digital-to-analogue converter (DAC) designed for use in hi-fi digital audio equipment such as Compact Disc players, digital tape or cassette recorders.

Features

• Selectable two-channel input format: offset binary or two’s complement
• Internal timing and control circuit
• TTL compatible digital inputs
• High maximum input bit-rate and fast settling time.

QUICK REFERENCE DATA

Supply voltages
pin 28 V pin 26 V pin 15 V
DD DD1 DD2
Supply currents
pin 28 I pin 26 I pin 15 I
DD DD1 DD2
Signal-to-noise ratio
(full scale sine-wave) at analogue outputs (AOL; AOR) S/N typ. 95 dB
Non-linearity
at T
Current settling time to ± 1 LSB t
= −20 to +70 °C typ.
amb
cs
Maximum input bit rate
at data input (pin 3) BR
max
Maximum clock frequency
at clock input (pin 2) f at clock input (pin 4) f
BCKmax SCKmax
Full scale temperature coefficient
at analogue outputs (AOL; AOR) TC Operating ambient temperature range T Total power dissipation P
FS amb tot
typ. 5 V typ. −5V typ. −15 V
typ. 45 mA typ. 45 mA typ. 25 mA
1
⁄
2
LSB
typ. 1 µs
min. 6 Mbits/s
min. 6 MHz min. 12 MHz
typ. ± 200 × 10−6 K
−1
−20 to +70 °C
typ. 850 mW

PACKAGE OUTLINE

28-lead DIL; plastic (with internal heat spreader) (SOT-117); SOT117-1; 1996 August 14.
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Dual 16-bit DAC TDA1541
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Fig.1 Block diagram.
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Dual 16-bit DAC TDA1541

PINNING

1 LE/WS*
latch enable input word select input
2 BCK* bit clock input
data left channel input
3 DATA L/DATA*
data input (selected format)
4 DATA R/SYS*
data right channel input
system clock input 5 GND (A) analogue ground 6 AOR right channel output 7 DECOU 8 DECOU 9 DECOU 10 DECOU
decoupling 11 DECOU 12 DECOU 13 DECOU 14 GND (D) digital ground 15 V
DD2
16 n.c. 17 n.c.
−15 V supply voltage
not connected 18 DECOU
19 DECOU 20 DECOU 21 DECOU
decoupling 22 DECOU 23 DECOU 24 DECOU 25 AOL left channel output 26 V 27 28 V
DD1
OB/TWC* mode selection input
DD
−5 V supply voltage
+5 V supply voltage
Fig.2 Pinning diagram.
* See Table 1 data selection input.
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Dual 16-bit DAC TDA1541

FUNCTIONAL DESCRIPTION

The TDA1541 accepts input sample formats in time multiplexed mode or simultaneous mode with any bit length. The most significant bit (MSB) must always be first. This flexible input data format allows easy interfacing with signal processing chips such as interpolation filters, error correction circuits, pulse code modulation adaptors and audio signal processors (ASP).
The high maximum input bit-rate and fast settling time facilitates application in 4 × oversampling systems (44,1 kHz to 176,4 kHz) with the associated simple analogue filtering function (low order, linear phase filter).
Input data selection (see also Table 1) With input
accompanied with a word select (WS) and a bit clock input (BCK) signal. A separate system clock input (SCK) is provided for accurate, jitter-free timing of the analogue outputs AOL and AOR.
With OB/TWC connected to VDD the mode is the same but data format must be in two’s complement. When input OB/TWC is connected to (V
(DATA R), accompanied with BCK and a latch-enable input (LE). With this mode selected the data must be in offset binary.
The format of data input signals is shown in figures 3, 4 and 5. True 16-bit performance is achieved by each channel using three 2-bit active dividers, operating on the dynamic element
matching principle, in combination with a 10-bit passive current-divider, based on emitter scaling. All digital inputs are TTL compatible.

Input data selection

−5 V simultaneous LE BCK DATA L DATA R 0 V time MUX OB WS BCK DATA OB SCK +5 V time MUX TWC WS BCK DATA TWC SCK
Where: LE = latch enable WS = word select BCK = bit clock DATA L = data left DATA R = data right DATA OB = data offset binary DATA TWC = data two’s complement MUX OB = multiplexed offset binary MUX TWC = multiplexed two’s complement
OB/TWC connected to ground, data input (offset binary format) must be in time multiplexed mode. It is
) the two channels of data (L/R) are input simultaneously via (DATA L) and
DD1
OB/TWC MODE PIN 1 PIN 2 PIN 3 PIN 4
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Dual 16-bit DAC TDA1541

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage ranges
pin 28 V pin 26 V
pin 15 V Crystal temperature range T Storage temperature range T Operating ambient temperature range T Electrostatic handling
(1)
Note
1. Discharging a 250 pF capacitor through a 1 kΩ series resistor.

THERMAL RESISTANCE

V
0 to +7 V
DD
0 to −7V
DD1
0 to −17 V
DD2
−55 to +150 °C
XTAL
−55 to +150 °C
stg
−20 to +70 °C
amb
−1000 to +1000 V
es
From junction to ambient R
= 35 K/W
th j-a
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Dual 16-bit DAC TDA1541

CHARACTERISTICS

= + 5 V; V
V
DD
Supply
Supply voltage ranges
pin 28 V
pin 26 −V
pin 15 −V Supply currents
pin 28 I
pin 26 −I
pin 15 −I Resolution Res − 16 − bits
Inputs
Input current (pin 3 and pin 4)
digital inputs LOW (< 0,8 V) I
digital inputs HIGH (> 2,0 V) I Input frequency
at clock input (pin 4) f
at clock input (pin 2) f
at data inputs (pin 3 and pin 4) f
at word select input (pin 1) f Input capacitance of digital inputs C
Oscillator
Oscillator frequency
with internal capacitor f Analogue outputs (AOL; AOR) Output voltage compliance V
Full scale current I Zero scale current ± I Full scale temperature coefficient
= −20 to +70 °CTC
T
amb
Linearity error integral
at T
at T
= 25 °CE
amb
= −20 to +70 °CE
amb
Linearity error differential
at T
at T
= 25 °CE
amb
= −20 to +70 °CEd1− tbf − LSB
amb
= −5 V; V
DD1
= −12 V; T
DD2
= + 25 °C; measured in Fig. 1; unless otherwise specified.
amb
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
DD
DD1 DD2
DD
DDI DD2
IL IH
SCK BCK DAT WS
I
osc
OC
FS
ZS
FS
1 1
d1
4,0 5,0 6,0 V 4,5 5,0 6,0 V 14 15 16 V
− 45 tbf mA
− 45 tbf mA
− 25 tbf mA
−−tbf mA
−−tbf µA
−−12 MHz
−−6 MHz
−−6 MHz
−−200 kHz
− 12 − pF
150 200 250 kHz
tbf − tbf mV 3,4 4,0 4,6 mA
− tbf − nA
−± 200 × 10-6− K
−1
−0,5 − LSB
−tbf − LSB
− 0,5 1 LSB
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Dual 16-bit DAC TDA1541
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Signal -to-noise ratio + THD* S/N 90 95 − dB Settling time to ± 1 LSB t
cs
Channel separation α 80 tbf − dB Unbalance between outputs ∆I Time delay between outputs t
FS
d
Power supply ripple rejection**
= +5 V RR − tbf − dB
V
DD
= −5 V RR − tbf − dB
V
DD1
= −15 V RR − tbf − dB
V
DD2
Signal-to-noise ratio
at bipolar zero S/N −−100 − dB Timing (see Figs 3, 4 and 5) Rise time t
Fall time t Bit clock cycle time t Bit clock HIGH time t Bit clock LOW time t Bit clock fall time to latch rise time t Bit clock rise time to latch fall time t Data set-up time to bit clock t Data hold time to bit clock t Data set-up time to system clock t Word select hold time to system clock t Word select set-up time to system clock t Bit clock fall time to system clock rise time t System clock rise time to bit clock fall time t System clock fall time to bit clock rise time t Bit clock rise time to system clock fall time t Latch enable LOW time t Latch enable HIGH time t
r f CY HB LB FBRL RBFL SDB HDB SDS HWS SWS FBRS RSFB FSRB RBFS LLE HLE
− 1 −µs
− 0,1 0,2 dB
−−1µs
−−35 ns
−−35 ns
160 −−ns 48 −−ns 48 −−ns 0 −−ns 0 −−ns 32 −−ns 0 −−ns 32 −−ns 0 −−ns 32 −−ns 32 −−ns 32 −−ns 50 −−ns 0 −−ns 20 −−ns 32 −−ns
* Signal-to-noise ratio + THD with 1 kHz full scale sinewave generated at a sampling rate of 176,4 kHz. ** V
= 1% of supply voltage and f
ripple
= 100 Hz.
ripple
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Dual 16-bit DAC TDA1541
Fig.3 Format of input signals; time multiplexed at f
SCK
= f
BCK
(I2S format).
Fig.4 Format of input signals; time multiplexed at f
November 1985 9
SCK
= 2 × f
BCK.
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Dual 16-bit DAC TDA1541
Fig.5 Format of input signals; simultaneous data.
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Dual 16-bit DAC TDA1541

PACKAGE OUTLINE

handbook, full pagewidth
DIP28: plastic dual in-line package; 28 leads (600 mil)

SOT117-1

seating plane
L
Z
28
1
pin 1 index
D
A
2
A
A
1
e
b
w M
b
1
15
E
14
c
M
(e )
M
E
1
H
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
A
A
UNIT
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
max.
mm
OUTLINE VERSION
SOT117-1
1 2
min.
max.
1.7
1.3
0.066
0.051
IEC JEDEC EIAJ
051G05 MO-015AH
b
b
1
0.53
0.38
0.020
0.014
0.32
0.23
0.013
0.009
REFERENCES
cD E weM
(1) (1)
36.0
35.0
1.41
1.34
November 1985 11
14.1
13.7
0.56
0.54
(1)
92-11-17 95-01-14
Z
max.
1.75.1 0.51 4.0
0.0670.20 0.020 0.16
L
3.9
15.80
3.4
15.24
EUROPEAN
PROJECTION
M
0.62
0.60
H
E
17.15
15.90
0.68
0.63
0.252.54 15.24
0.010.10 0.60
ISSUE DATE
e
1
0.15
0.13
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Dual 16-bit DAC TDA1541
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in
“IC Package Databook”
our
Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
(order code 9398 652 90011).
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
stg max
). If the
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
November 1985 12
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