Computers
Telecom Racks
Power Supplies / UPS* / Amplifiers
■Copiers / Office Electronics
■Consumer Electronics
■Process Control
GENERAL DESCRIPTION
The TCN75 is a serially programmable temperature
sensor that notifies the host controller when ambient tem-
perature exceeds a user-programmed setpoint. Hysteresis
is also programmable. The INT/CMPTR output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. Communication
with the TCN75 is accomplished via a two-wire bus that is
compatible with industry standard protocols. This permits
reading the current temperature, programming the setpoint
and hysteresis, and configuring the device.
The TCN75 powers up in Comparator Mode with a
default setpoint of 80°C with 5°C hysteresis. Defaults allow
independent operation as a stand-alone thermostat. A shutdown command may be sent via the 2-wire bus to activate
the low-power standby mode. Address selection inputs
allow up to eight TCN75's to share the same 2-wire bus for
multi-zone monitoring.
All registers can be read by the host and the INT/
CMPTR output's polarity is user programmable. Both polled
and interrupt driven systems are easily accommodated.
Small physical size, low installed cost, and ease of use make
the TCN75 an ideal choice for implementing sophisticated
system management schemes.
ORDERING INFORMATION
Supply Junction
Part No.Voltage (V) Package Temp. Range
TCN75-3.3MOA3.38-Pin SOIC– 55°C to +125°C
TCN75-5.0MOA5.08-Pin SOIC– 55°C to +125°C
T
CN75-3.3MPA3.38-Pin PDIP– 55°C to +125°C
TCN75-5.0MPA5.08-Pin PDIP– 55°C to +125°C
TCN75-3.3MUA3.38-MSOP– 55°C to +125°C
TCN75-5.0MUA5.08-MSOP– 55°C to +125°C
FUNCTIONAL BLOCK DIAGRAM
9 Bit
∆Σ
A/D
Temp
DD
SDA
SCL
Sensor
A
0
A
1
A
2
V
TCN75-04 6/16/97
Converter
Register Set
Configuration
Temperature
Two Wire
Serial Port
Interface
TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.
T
T
Control
SET
HYST
Logic
TCN75
INT/CMPTR
PIN CONFIGURATIONS
8-Pin Plastic DIP
1
SDAV
2
SCL
INT/CMPTRA1
INT/CMPTR
1
GND
SDA
SCL
GND
3
TCN75MPA
4
8-Pin SOIC
1
2
TCN75MOA
3
4
8
7
6
5
8
7
6
5
DD
A0
A2
V
DD
A0
A1
A2
SDA
SCL
INT/CMPTR
GND
8-Pin MSOP
1
2
TCN75MUA
3
4
V
8
DD
7
A0
6
A1
5
A2
Page 2
PRELIMINARY INFORMATION
TCN75
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONIT OR
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) .................................................6.0V
*This is a stress rating only and functional operation of this device at these
or any other conditions above those indicated in the operations sections of
this specification is not implied.
SymbolParameterTest ConditionsMinTypMaxUnit
Power Supply
V
I
I
DD
DD
DD1
Power Supply Voltage2.7—5.5V
Operating Current
Serial Port Inactive (T
= TJ = 25°C)
A
—0.250—mA
Serial Port Active——1.0
Standby Supply CurrentShutdown Mode, Serial Port Inactive—1—µA
(TA = TJ = 25°C)
INT/CMPTR Output
I
OL
t
TRIP
V
OL
Sink Current: INT/CMPTR, SDANote 1—14mA
Outputs
INT/CMPTR Response TimeUser Programmable1—6t
CONV
Output Low VoltageIOL = 4.0mA——0.8V
Temp-to-Bits Converter
∆TTemperature Accuracy (Note 2)– 55°C ≤ TA ≤ +125°C—±3—°C
V
= 3.3V : TCN75-3.3MOA,
DD
TCN75-3.3MPA, TCN75-3.3MUA
= 5.0V: TCN75-5.0MOA,
V
DD
TCN75-5.0MPA, TCN75-5.0 MUA
25°C ≤ TA ≤ 100°C—±0.5±2°C
t
CONV
T
SET(PU)
T
HYST(PU)
Conversion Time—100—msec
TEMP Default ValuePower Up—80—°C
T
Serial Port Frequency0100400kHz
Low Clock Period1250——nsec
High Clock Period1250——nsec
SCL and SDA Rise Time——250nsec
SCL and SDA Fall Time——250nsec
Start Condition Setup Time1250——nsec
(for repeated Start Condition)
2
Page 3
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONIT OR
NOTES: 1. Output current should be minimized for best temperature accuracy. Power dissipation within the TCN75 will cause self-heating and
Start Condition Hold Time1250——nsec
Data in Setup Time to SCL High100——nsec
Data in Hold Time after SCL Low0——nsec
Stop Condition Setup Time1250——nsec
Bus Free Time Prior to New1250——nsec
Transition
temperature drift. At maximum rated output current and saturation voltage, 4mA and 0.8V, respectively, the error amounts to 0.352°C for the
PDIP, and 0.544°C for the SOIC.
2. All part types of the TCN75 will operate properly over the wider power supply range of 2.7V to 5.5V. Each part type is tested and specified
for rated accuracy at its nominal supply voltage. As VDD varies from the nominal value, accuracy will degrade 1°C/V of VDD change.
3. Human body model, 100pF discharged through a 1.5k resistor, machine model, 200pF discharged directly into each pin.
PIN DESCRIPTION
Pin NumberSymbolDescription
1SDABidirectional Serial Data.
2SCLSerial Data Clock Input.
3INT/CMPTRInterrupt or Comparator Output.
4GNDSystem Ground.
5A
6A
7A
8VDDPower Supply Input.
Bidirectional. Serial data is transferred in both directions
using this pin.
Serial Clock (SCL)
Input. Clocks data into and out of the TCN75.
INT/CMPTR
Open Collector, Programmable Polarity. In Comparator
Mode, unconditionally driven active any time temperature
exceeds the value programmed into the T
CMPTR will become inactive when temperature subsequently falls below the T
Programmer's Model.
setting. (See
HYST
) In Interrupt Mode, INT/CMPTR is
also made active by TEMP exceeding T
ally reset to its inactive state by reading any register via the
2-wire bus. If and when temperature falls below T
CMPTR is again driven active. Reading any register will
clear the T
TCN75-04 6/16/97
interrupt. In Interrupt Mode, the INT/CMPTR
HYST
register. INT/
SET
Register Set and
; it is uncondition-
SET
HYST
, INT/
output is unconditionally reset upon entering Shutdown
Mode. If programmed as an active-low output, it can be
wire-ORed with any number of other open collector devices.
Most systems will require a pull-up resistor for this configuration.
Note that current sourced from the pull-up resistor
causes power dissipation and may cause internal heating of
the TCN75. To avoid affecting the accuracy of ambient
temperature readings, the pull-up resistor should be made
as large as possible. INT/CMPTR's output polarity may be
programmed by writing to the INT/CMPTR POLARITY bit in
the CONFIG register. The default is active low.
Address (A2, A1, A0)
Inputs. Sets the three least significant bits of the TCN75
8-bit address. A match between the TCN75's address and
the address specified in the serial bit stream must be made
to initiate communication with the TCN75. Many protocolcompatible devices with other addresses may share the
same 2-wire bus.
Slave Address
The four most significant bits of the Address Byte (A6,
A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and
3
Page 4
PRELIMINARY INFORMATION
TCN75
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONIT OR
A0 in the serial bit stream must match the states of the A2,
A1 and A0 address inputs for the TCN75 to respond with an
Acknowledge (indicating the TCN75 is on the bus and ready
to accept data). The Slave Address is represented by:
TCN75 Slave Address
1001A2A1A0
MSBLSB
Comparator/Interrupt Modes
INT/CMPTR behaves differently depending on whether
the TCN75 is in Comparator Mode or Interrupt Mode.
Comparator Mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds
T
. When in Comparator Mode, INT/CMPTR will remain
SET
active until TEMP falls below T
, whereupon it will reset
HYST
to its inactive state. The state of INT/CMPTR is maintained
in shutdown mode when the TCN75 is in comparator mode.
In Interrupt Mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below T
, until any register is
HYST
read via the 2-wire bus. Interrupt Mode is better suited to
interrupt driven microprocessor-based systems. The INT/
CMPTR output may be wire-OR'ed with other interrupt
sources in such systems. Note that a pull-up resistor is
necessary on this pin since it is an open-drain output.
Entering Shutdown Mode will unconditionally reset INT/
CMPTR when in Interrupt Mode.
SHUTDOWN MODE
When the appropriate bit is set in the configuration
register (CONFIG) the TCN75 enters its low-power shutdown mode (IDD = 1µA, typical) and the temperature-todigital conversion process is halted. The TCN75's bus
interface remains active and TEMP, T
SET
, and T
HYST
may be
read from and written to. Transitions on SDA or SCL due to
external bus activity may increase the standby power consumption. If the TCN75 is in Interrupt Mode, the state of INT/
CMPTR will be RESET upon entering shutdown mode.
Fault Queue
To lessen the probability of spurious activation of INT/
CMPTR the TCN75 may be programmed to filter out transient events. This is done by programming the desired value
into the Fault Queue. Logic inside the TCN75 will prevent the
device from triggering INT/CMPTR unless the programmed
number of sequential temperature-to-digital conversions
yield the same qualitative result. In other words, the value
reported in TEMP must remain above T
for the consecutive number of cycles programmed in the
Fault Queue. Up to a six-cycle "filter" may be selected. See
Register Set and Programmer's Model
or below T
SET
.
HYST
Serial Port Operation
The Serial Clock input (SCL) and bidirectional data port
(SDA) form a 2-wire bidirectional serial port for programming
and interrogating the TCN75. The following conventions are
used in this bus scheme:
TCN75 Serial Bus Conventions
TermExplanation
TransmitterThe device sending data to the bus.
ReceiverThe device receiving data from the bus.
MasterThe device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
SlaveThe device addressed by the master.
StartA unique condition signaling the beginning of a
transfer indicated by SDA falling (High-Low) while
SCL is high.
StopA unique condition signaling the end of a transfer
indicated by SDA rising (Low - High) while SCL is
high.
ACKA Receiver acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock pulse
for the ACK cycle.
NOT BusyWhen the bus is idle, both SDA & SCL will
remain high.
Data ValidThe state of SDA must remain stable during the
High period of SCL in order for a data bit to be
considered valid. SDA only changes state while
SCL is low during normal data transfers. (See
Start and Stop conditions)
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TCN75
operates as a Slave. This serial protocol is illustrated in
Figure 2. All data transfers have two phases; and all bytes
are transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes
a Read/Write selection bit. Each access must be terminated
by a Stop Condition (STOP). A convention called
edge
(ACK) confirms receipt of each byte. Note that SDA
can change only during periods when SCL is LOW (SDA
changes while SCL is HIGH are reserved for Start and Stop
Conditions).
Start Condition (START)
The TCN75 continuously monitors the SDA and SCL
lines for a start condition (a HIGH to LOW transition of SDA
while SCL is HIGH), and will not respond until this condition
is met.
always
Acknowl-
TCN75-04 6/16/97
4
Page 5
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONIT OR
PRELIMINARY INFORMATION
TCN75
Address Byte
Immediately following the Start Condition, the host must
next transmit the address byte to the TCN75. The four most
significant bits of the Address Byte (A6, A5, A4, A3) are fixed
to 1001(B). The states of A2, A1 and A0 in the serial bit
stream must match the states of the A2, A1 and A0 address
inputs for the TCN75 to respond with an Acknowledge
(indicating the TCN75 is on the bus and ready to accept
data). The eighth bit in the Address Byte is a Read-Write Bit.
This bit is a 1 for a read operation or 0 for a write operation.
Acknowledge (ACK)
Acknowledge (ACK) provides a positive handshake
between the host and the TCN75. The host releases SDA
after transmitting eight bits then generates a ninth clock
cycle to allow the TCN75 to pull the SDA line LOW to
acknowledge that it successfully received the previous eight
bits of data or address.
Data Byte
After a successful ACK of the address byte, the host
must next transmit the data byte to be written or clock out the
data to be read. (See the appropriate timing diagrams.) ACK
will be generated after a successful write of a data byte into
the TCN75.
over the power supply voltage range of 2.7V to 5.5V, but
with a lower measurement accuracy. Figure 2 shows the
worst case temperature measurement error for the
TCN75CO_-3 operated at a power supply voltage of 5V ±
10%. Figure 3 shows the worst case temperature measurement error for the TCN75CO_-3 operated at a power supply
voltage of 3.3V ±10%.
±5
±4
±3
ERROR (°0)
±2
±1
203550658012595110
TCN75 Case Temeprature (°C)
Figure 2. TCN75CO_-3 Measurement Error at V
= 5V ± 10%
DD
Stop Condition (STOP)
Communications must be terminated by a stop condition (a LOW to HIGH transition of SDA while SCL is HIGH).
The Stop Condition must be communicated by the transmitter to the TCN75.
Power Supply
To minimize temperature measurement error, the
TCN75VO_-3 is factory calibrated at a supply voltage of
3.3V ±5V and the TCN75CO_-5 is factory calibrated at a
supply voltage of 5V ±5%. Either device is fully operational
(3V to 5.5V)
+V
DD
C
Address
(Set as Desired)
2
I
C Interface
A
SDA
SCL
Bypass
8
A
A
7
0
6
1
5
2
TCN75
1
2
4
0.1µF Recommended
Unless Device is Mounted
Close to CPU
3
INT/CMPTR
TO PROCESSOR
±5
±4
±3
ERROR (°0)
±2
±1
203550658012595110
TCN75 Case Temeprature (°C)
Figure 3. TCN75CO_-5 Measurement Error at V
= 3.3V ± 10%
DD
TCN75-04 6/16/97
Figure 1. Typical Application
5
Page 6
PRELIMINARY INFORMATION
TCN75
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONIT OR
1
00
1
Start
by
Master
Address Byte
(a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, TOS, T
represents one-half degree (Celsius). The value is in 2's complement binary format such that a reading of 000000000b
corresponds to 0°C. Examples of this temperature to binary
value relationship are shown in the following table.