Datasheet TC7109/A Datasheet
TC7109/A
12-Bit A-Compatible Analog-to-Digital Converters
Features:
• Zero Integrator Cycle for Fast Recovery from
Input Overloads
• Eliminates Cr oss-Talk in Multiplexed Systems
• 12-Bit Plus Sign Integrating A/D Converter with
Over Range In dication
• Sign Magnitude Coding Format
• True Differential Signal Input and Differential
Referenc e Input
• Low Noise: 15V
• Input Current: 1pA Typ.
• No Zero Adjustment needed
• TTL Compatible, Byte Organized Tri-State
Outputs
• UART Handsha k e Mode for simple Serial Data
Transmissions
P-P
Typ.
Device Selection Table
Part Number
(TC7109X)*
TC7109CKW 44-Pin PQFP 0°C to +70°C
TC7109CLW 44-Pin PLCC 0°C to +70°C
TC7109CPL 40-Pin PDIP 0°C to +70°C
TC7109IJL 40-Pin CERDIP -25°C to +85°C
*The “A” version has a higher I
Package
OUT
Temperature
Range
on the digital lines.
General Description:
The TC7109A is a 12-bit plus sign, CMOS low power
Analog-to- Digita l Con verter (ADC ). O nly ei ght pas sive
components and a crystal are required to form a
complete dual slope integrating ADC.
The improved V
features make it a n attractive per-c hannel altern ative to
analog multiplexing for many data acquisition applications. These features include typical input bias current
of 1pA, drift of less than 1V/°C, input noise typically
15V
erence allow measurement of bridge type transducers,
such as load cells, strain gauges and temperature
transducers.
The TC7109A provides a versatile digital interface. In
the Direct mode, Chip Select and HIGH
enable control par allel bu s in terface . In the Handsh ake
mode, the TC7109A will ope rate with in dustry sta ndard
UARTs i n controlling s erial data tra nsmission – id eal for
remote data log ging. Contro l and monito ring of conv ersion timing is provided by the RUN/HOLD
Status output.
For applications requiring more resolution, see the
TC500, 15-bit plus sign ADC dat a sheet. The TC 7109A
has improved over range recovery performance and
higher output drive cap abil ity th an the origina l T C7109.
All new (or existing) designs should specify the
TC7109A wherever possible.
, and auto-zero. True differential input and ref-
P-P
source current and other TC7109A
OH
/LOW byte
input and
2002-2012 Microchip Technology Inc. DS21456D-page 1
TC7109/A
Package Type
12
OR
B
44 43 42 41 39 3840
B
1
11
B
2
10
B
3
9
B
4
8
B
5
7
6
NC
B
7
6
B
5
B
4
B
3
B
2
12 13 14 15 17 18
1
B
TEST
44-Pin PQFP
STATUS
POL
GND
NC
TC7109ACKW
TC7109CKW
16
LBEN
NC
HBEN
CE/LOAD
REF CAP-
REF IN-
V+
37 36 35 34
19 20 21 22
MODE
OSC IN
OSC OUT
REF IN+
REF CAP+
33
32
31
30
29
28
27
268
259
2410
2311
BUFF
OSC SEL
OSC OUT
B
B
NC
11
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
IN HI
IN LO
COMMON
INT
AZ
NC
BUFF
REF OUT
V-
SEND
RUN/HOLD
40-Pin PDIP/CERDIP
44-Pin PLCC
12
B
6543 1442
7
8
9
10
11
12
13
18 19 20 21 23 24
1
B
OR
TEST
POL
LBEN
STATUS
TC7109ACLW
TC7109CLW
HBEN
GND
22
CE/LOAD
V+
NC
43 42 41 40
25 26 27 28
NC
MODE
REF CAP-
REF IN-
OSC IN
OSC OUT
REF IN+
REF CAP+
39
38
37
36
35
34
33
3214
3115
3016
2917
BUFF
OSC SEL
OSC OUT
IN HI
IN LO
COMMON
INT
AZ
NC
BUFF
REF OUT
V-
SEND
RUN/HOLD
GND
1
STATUS
CE/LOAD
POL
OR
B
B
B
B
B
B
B
B
B
B
B
B
TEST
LBEN
HBEN
2
3
4
5
12
6
11
10
7
TC7109A
8
9
9
8
10
7
6
11
12
5
13
4
14
3
15
2
16
1
17
18
19
20
NC = No internal connection
TC7109
40
V+
39
REF IN-
38
REF CAP-
37
REF CAP+
36
REF IN+
35
IN HI
IN LO
34
33
COMMON
32
INT
31
AZ
30
BUFF
REF OUT
29
28
V-
27
SEND
26
RUN/HOLD
25
BUFF OSC OUT
24
OSC SEL
23
OSC OUT
22
OSC IN
21
MODE
DS21456D-page 2 2002-2012 Microchip Technology Inc.
Typical Application
Input
High
AZ
BUFF
C
AZ
INT
Buffer
Integrator
AZZIAZ
ZI
DE
(+)
AZ
INT
AZ
Comparator
Comp
Out
35
3130
C
REF
AZ
DE (±)
ZI
33
34
Common
Input Low
INT
37 36
REF
IN+
DE
(–)
DE
(–)DE(+)
R
INT
C
INT
3839
REF
CAP-
REF
CAP+
ZI
6.2V
10mA
28 40
V+
V-
29
REF
OUT
17 3 4 5 6 7 8 9 10 11 12 13 14
226222324
25
21
To Analog
Section
Comp Out
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
Handshake
Logic
15 16
27
18
19
20
LBEN
HBEN
CE/LOAD
1
GND
14 Latches
12-Bit Counter
16 Three-State Outputs
Send
Mode
BUFF
OSC
OUT
OSC
SEL
OSC
OUT
OSC
IN
RUN/
HOLD
Status
POL
OR
TEST
High Order
Byte Inputs
Low Order
Byte Inputs
TC7109A
REF
IN-
B12B11B
10
B9B8B7B6B5B4B3B2B
1
Latch
Clock
32
+
+
–
–
+
–
TC7109/A
2002-2012 Microchip Technology Inc. DS21456D-page 3
TC7109/A
1.0 ELECTRICAL
CHARACTERISTICS
*Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only and functional
operation of the devic e at these or an y other con ditions
Absolute Maximum Ratings*
Positive Supply Voltage (GND to V+)..................+6.2V
Negative Supply Voltage (GND to V-).....................-9V
Analog Input Voltage (Low to High)
(Note 1)
....V+ to V-
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
Reference Input Voltage:
(Low to High) (Note 1).............................V+ to V-
Digital Input Voltage:
(Pins 2-27) (Note 2)...........................GND – 0.3V
Power Dissipation, T
< 70°C (Note 3)
A
CERDIP ......................................................2.29W
Plastic DIP ..................................................1.23W
PLCC ..........................................................1.23W
PQFP..........................................................1.00W
Operating Tempe r atu re Range
Plastic Package (C) .........................0°C to +70°C
Ceramic Package (I).....................-25°C to +85°C
Storage Temperature Range..............-65°C to +150°C
TC7109/TC7109A ELECTRICAL SPECIFICATIONS
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated.
Symbol Parameter Min Typ Max Unit Test Conditions
Analog
Overload Recovery Time (TC7109A) — 0 1 Measurement
Zero Input Reading -0000
Ratio Metric Reading 3777
NL Non-Linearity (Max Deviation
CMRR Input Common Mode
V
CMR
e
N
I
IN
TC
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.
from Best Straight Line Fit)
Rollover Error (Difference in Reading for
Equal Positive and Inputs near
(Full Scale)
Rejection Ratio
Common Mode Voltage Range V- +1.5 — V+ -1.5 V Input High, Input Low and
Noise (P-P Value Not
Exceeded 95% of Time)
Leakage Current at Input — 1 10 pA VIN, All Packages: +25°C
Zero Reading Drift — 0.2 1 V/°C VIN = 0V
ZS
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
±00008 +00008Octal Reading VIN = 0V; Full Scale = 409.6mV
8
3777
8
4000
-1 ±0.2 +1 Count Full Scale = 409.6mV to 2.048V
-1 ±0.02 +1 Count Full Scale = 409.6mV to
—50 — V/V V
—15 — VV
— 20 100 pA C Device: 0°C T
— 100 250 pA I Device: -25°C T
40008Octal Reading VIN = V
8
8
Cycle
REF
V
= 204.8mV
REF
Over Full Operating
Temperature Range
2.048V Over Full Operating
Temperature Range
±1V, VIN = 0V
CM
Full Scale = 409.6mV
Common Pins
= 0V, Full Scale = 409.6mV
IN
+70°C
A
+85°C
A
DS21456D-page 4 2002-2012 Microchip Technology Inc.
TC7109/A
TC7109/TC7109A ELECTRICAL SPECIFICATIONS (Continued)
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V , TA = +25°C, unless otherwise indicated.
Symbol Parameter Min Typ Max Unit Test Conditions
TC
+
I
I
S
V
REF
TC
Digital
V
OH
V
OL
V
IH
V
IL
t
W
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.
Scale Factor Temperature Coefficient — 1 5 V/°C VIN = 408.9mV = >7770
FS
Supply Current (V+ to GND) — 700 1500 AV
Reading, Ext Ref = 0ppm/°C
= 0V, Crystal Oscillator
IN
3.58MHz Test Circuit
Supply Current (V+ to V-) — 700 1500 A Pins 2-21, 25, 26, 27, 29 Open
Reference Out Voltage -2.4 -2.8 -3.2 V Referenced to V+, 25k
Between V+ and Ref Out
Ref Out Temperature Coefficient — 80 — ppm/°C 25k Between V+ and Ref Out
REF
Output High Voltage
= 700A
I
OUT
3.5 4.3 — V TC7109: I
Output Low Voltage — 0.2 0.4 AI
0°C T
+70°C
A
OUT
= 100A
Pins 3 -16, 18, 19, 20
TC7109A: I
= 1.6mA
OUT
OUT
= 700A
Output Leakage Current — ±0.01 ±1 A Pins 3 -16 High-Impedance
Control I/O Pull-up Current — 5 — F Pins 18, 19, 20 V
OUT
Mode Input at GND
Control I/O Loading — — 50 pF HBEN
, Pin 19; LBEN, Pin 18
Input High Voltage 2.5 — — V Pins 18 -21, 26, 27
Referenced to GND
Input Low Voltage — — 1 V Pins 18-21, 26, 27
Referenced to GND
Input Pull-up Current —
—
25
5
—
—
A
A
Pins 26, 27; V
Pins 17, 24; V
Input Pull-down Current — 1 — A Pins 21, V
Oscillator Output Current, High — 1 — mA V
Oscillator Output Current, Low — 1.5 — mA V
Buffered Oscillator Output Current High — 2 — mA V
Buffered Oscillator Output Current Low — 5 — mA V
OUT
OUT
OUT
OUT
– 2.5V
– 2.5V
– 2.5V
– 2.5V
= V+ – 3V
OUT
= V+ – 3V
OUT
= GND = +3V
OUT
Mode Input Pulse Width 60 — — nsec
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
= V+ – 3V
8
HANDLING PRECAUTIONS: These devices are CMOS and mu st be handle d correctly to prevent dam age. Package
and store only in conductive foam, antistatic tubes, or other conducting material. Use proper antistatic handling pro-
cedures. Do not connect in circuits under “power-on” conditions, as high transients may cause permanent damage.
2002-2012 Microchip Technology Inc. DS21456D-page 5
TC7109/A
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
(40-Pin PDIP)
1 GND Digital ground, 0V, ground return for all digital logic.
2 STATUS Output HIGH during integrate and de-integrate until data is latched. Output LOW when
3 POL Polarity – High for positive input.
4 OR Over Range – High if over ranged (Three-State Data bit).
5B
6B
7B
8B
9B
10 B
11 B
12 B
13 B
14 B
15 B
16 B
17 TEST Input High – Normal operation. Input LOW – Forces all bit outputs HIGH.
18 LBEN
19 HBEN
20 CE
21 MODE Input LOW – Direct Output mode where CE
Symbol Description
analog section is in auto-zero or zero integrator configuration.
12
11
10
9
8
7
6
5
4
3
2
1
Bit 12 (Most Significant bit) (Three-State Data bit).
Bit 11 (Three-State Data bit).
Bit 10 (Three-State Data bit).
Bit 9 (Three-State Data bit).
Bit 8 (Three-State Data bit).
Bit 7 (Three-State Data bit).
Bit 6 (Three-State Data bit).
Bit 5 (Three-State Data bit).
Bit 4 (Three-State Data bit).
Bit 3 (Three-State Data bit).
Bit 2 (Three-State Data bit).
Bit 1 (Least Significant bit) (Three-State Data bit).
Note: This input is used for test purposes only.
Low Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates low order byte outputs, B
. With MODE (Pin 21) HIGH, this pin serves as
1–B8
low byte flag output used in Handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)
High Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates high order byte outputs, B
, POL, OR. With M O D E (Pin 21) HIGH , th i s
9–B12
pin serves as high byte flag output used in Handshake mode. See Figures 3-7, 3-8, and 3-9.
/LOAD Chip Enable/Load – with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable.
When HIGH, B
, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load
1–B12
strobe is used in handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)
/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin
18) act as inputs directly controlling byte outputs. Input Pulsed HIGH - Causes immediate
entry into Handshake mode and output of data as in Figure 3-9.
Input HIGH – enables CE
/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs,
Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9
at conversions completion.
22 OSC IN Oscillator Input.
23 OSC OUT Oscillator Output.
24 OSC SEL O s cillator Select – Input HIGH configures OSC IN, OSC OUT, BUFF OSC OUT as RC
oscillator – clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW
configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency
at BUFF OSC OUT.
25 BUFF OSC OUT Buffered Oscillator Output.
26 RUN/HOLD
Input HIGH – Conversions continuously performed every 8192 clock pulses.
Input LOW – Conversion in progress completed; converter will stop in auto-zero seven
counts before integrate.
27 SEND Input - Used in Handshake mode to indicate ability of an external device to accept data.
Connect to V+ if not used.
28 V- Analog Negative Supply – Nominally -5V with respect to GND (Pin 1).
29 REF OUT Reference Voltage Output – Nominally 2.8V down from V+ (Pin 40).
DS21456D-page 6 2002-2012 Microchip Technology Inc.
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-Pin PDIP)
30 BUFF Buffer Amplifier Output.
31 AZ Auto-Zero Node – Inside foil of C
32 INT Integrator Output – Outside foil of C
33 COMMON Analog Common – System is auto-zeroed to COMMON.
34 IN LO Differential Input Low Side.
35 IN HI Differential Input High Side.
36 REF IN+ Differential Reference Input Positive.
37 REF CAP+ Reference Capacitor Positive.
38 REF CAP- Reference Capacitor Negative.
39 REF IN- Differential Reference Input Negative.
40 V+ Positive Supply Voltage – Nominally +5V with respect to GND (Pin 1).
Note: All Digital levels are positive true.
Symbol Description
.
AZ
.
INT
TC7109/A
2002-2012 Microchip Technology Inc. DS21456D-page 7
TC7109/A
3.0 DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP.)
3.1 Analog Section
The Typical Application diagram on page 3 shows a
block diagram of the analog section of the TC7109A.
The circuit will perform conversions at a rate determined by the clock frequency (8192 clock periods per
cycle), when the RUN/HOLD input is left open or
connected to V+. Each measurement cycle is divided
into four phases, as shown in Figure 3-1. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3)
Reference De-integrate (DE), and (4) Zero Integrator
(ZI).
3.1.1 AUTO-ZERO PHASE
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The refere nce cap acitor is charged to the reference voltage. A feedback loop is closed around the
system to charge the auto-z ero ca pac itor, CAZ, to compensate for offset voltage in the buffer amplifier, integrator, and comparator. Since the comparator is
included in the loop, the AZ accuracy is limited only by
the noise of the syste m. The o ffs et referre d to the input
is less than 10V.
3.1.2 SIGNAL INTEGRATE PHASE
The buffer and integrator inpu ts are removed from common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is
placed in series in the loop to provide an equal and
opposite compensating offset voltage. The differential
voltage between input high and input low is integrated
for a fixed time of 204 8 clo ck per iods. A t the en d of this
phase, the polarity of the integrated signal is
determined. If the input signal has no return to the
converter’s power supply, input low can be tied to
analog common to establish the correct Common
mode voltage.
3.1.3 DE-INTEGRATE PHASE
Input high is connected across the previously charged
reference capacitor and input low is internally
connected to analog common. Circuitry within the chip
ensures the cap acitor will be co nnected with th e correct
polarity to cause the integrator output to return to the
zero crossing (established by auto-zero), with a fixed
slope. The time, represented by the number of clock
periods counted for the output to return to zero, is
proportional to the input signal .
3.1.4 ZERO INTEGRATOR PHASE
The ZI phase only occurs when an input over range
condition exists. The function of the ZI phase is to
eliminate residual charge on the integrator capacitor
after an over range measurement. Unless removed,
the residual charge will be transferred to the auto-zero
capacitor and cause an error in the succeeding
conversion.
The ZI phase virtually eliminates hysteresis, or “crosstalk” in multiplexed systems. An over range input on
one channel will not ca use an error on the n ext channel
measured. This feature is especially useful in thermocouple measurements, where unused (or broken
thermocouple) inputs are pulled to the positive supply
rail.
During ZI, the reference cap acitor is ch arged to the reference voltage. The signal inputs are disconnected
from the buffer and integrator . The comp arator output is
connected to the buffer input, causing the integrator
output to be driven rapidly to 0V (Figure 3-1). The ZI
phase only occurs followin g an over range and l asts f or
a maximum of 1024 clock periods.
3.1.5 DIFFERENTIAL INPUT
The TC7109A has been optimized for operation with
analog common near digi t al gr oun d. Wit h +5V an d -5V
power supplies, a full ±4V full scale integrator swing
maximizes the analog section’s performanc e.
A typical C M RR o f 86 dB is ac hi e ve d fo r i np u t diffe r en tial voltages anywhere within the typical Common
mode range of 1V below the positive supply, to 1.5V
above the negative supply. However, for optimum performance, the IN HI and IN LO inputs should not come
within 2V of either supply rail. Since the integrator also
swings with the Common mode voltage, care must be
exercised to ensure the integrator output does not saturate. A worst-case condition is near a full scale negative differential input voltage with a large positive
Common mode voltage. The negative input signal
drives the integrator positive when most of its swing
has been used up by the positive Common mode voltage. In such cases, the integrator swing can be
reduced to less than the recommended ±4V full scale
value, with some loss of accuracy. The integrator
output can swing to withi n 0 .3V of either s upply w itho ut
loss of linearity.
DS21456D-page 8 2002-2012 Microchip Technology Inc.
TC7109/A
3.1.6 DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Rollover voltage is the main source of Common mode
error, caused by the reference capacitor losing or gaining charge, due to stray capacity on its nodes. With a
large Common mode voltage, the reference capacitor
can gain charge (increase voltage) when calle d upon to
de-integrate a positive signal and lose charge
(decrease voltage) when called upon to de-integrate a
negative i nput signal. T his difference in reference for
(+) or (–) input volta ges will ca us e a ro llover error. This
error can be held to less than 0.5 coun t, worst-case , by
using a large reference capacitor in comparison to the
stray capacitance. To minimize rollover error from
these sources, keep the reference Common mode
voltage near or at analog common.
3.2 Digital Section
The digital section is shown in Figure 3-2 and includes
the clock oscillator and scaling circuit, a 12-bit binary
counter with output latches and TTL compatible threestate output drivers, UART handshake logic, polarity,
over range, and control logic. Logic levels are referred
to as LOW or HIGH.
Inputs driven from TTL gates should have 3k to 5k
pull-up resistors added for maximum noise immunity.
For minimum power consumption, all inputs should
swing from GND (LOW) to V+ (HIGH).
3.2.1 STATUS OUTPUT
During a conversion cy cl e, th e Stat us o utp ut go es hig h
at the beginning of signal integrate and goes low onehalf clock period after new data from the conversion
has been stored in the output latc hes (see Figu re3-1).
The signal may be used as a “data valid” flag to drive
interrupts, or for monitoring the status of the converter.
(Data will not change while status is low.)
3.2.3 RUN/HOLD INPUT
With the RUN/HOLD input high, or open, the circuit
operates normally as a dual slope ADC, as shown in
Figure 3-1. Conversion cycles operate continuously
with the out put latche s updated afte r zero crossi ng in
the De-integrate mode. An internal pull-up resistor is
provided to ensure a HIGH level with an open input.
The RUN/HOLD
sion time. If RUN/HOLD
crossing in the De-integrate mode, the circuit will jump
to auto-zero and eliminat e that porti on of time normall y
spent in de-integrate.
If RUN/HOLD
complete with mini mum t im e i n d e-i nteg rate . It wil l s t ay
in auto-zero for the minim um time and wait in auto-zero
for a HIGH at the RUN/HOLD
Figure 3-3, the Status output will go HIGH, 7 clo ck periods after RUN/HOLD
converter will begin the integrate phase of the next
conversion.
The RUN/HOLD
interface. The converter ma y be held at Idle in autozero with RUN/HOLD LOW. The conversion is started
when RUN/HOLD
valid when the Status output goes LOW (or is transferred to the UART; see “Handshake Mode”). RUN/
may now go LOW, terminating de-integrate and
HOLD
ensuring a minimum auto-zero time before stopping to
wait for the next conversion. Conv ersion time can be
minimized by ensuring RUN/HOLD
de-integrate, after zero crossing, and goes HIGH after
the hold point is reached.
The required activity on the RUN/HOLD
provided by connecting it to the buffered oscillator
output. In this mode, the input value measured
determines the conversion time.
input may be used to shorten conver-
goes LOW any tim e a fter zero
stays or goes LO W, the conversion wi ll
input. As shown in
is changed to HIGH, and the
input allows controlled conversion
goes HIGH, and the new data is
goes LOW duri ng
input can be
3.2.2 MODE INPUT
The Output mode of the converter is controlled by the
MODE input. The converter is in its “Direct” Output
mode, when the MODE input is LOW or left open. The
output data is directly accessible under the control of
the chip and byte enable inputs (this input is provided
with a pull- down resi stor to en sure a LO W level wh en
the pin is left open). When the MODE input is pulsed
high, the converter e nte rs th e U ART Handshake mode
and outputs the dat a in 2 bytes , then return s to “Direct”
mode. When the MODE input is kept HIGH, the
converter will output data in the Handshake mode at
the end of every conversion cycle. With MODE = 0
(direct bus transfer), the send input should be tied to
V+. (See “Handshake Mode”.)
2002-2012 Microchip Technology Inc. DS21456D-page 9
TC7109/A
Internal Clock
Integrator Output
for Normal Input
Integrator
Saturates
Internal Latch
Integrator Output
for Over Range Input
No Zero Crossing
ZI
AZ
Zero Integrator
Phase forces
Integrator Output
to 0V
Zero Crossing
Occurs
Zero Crossing
Detected
INT
Phase II
Status Output
AZ
Phase I
DE
Phase III
AZ
Fixed
2048
Counts
2048
Counts
Min.
4096
Counts
Max
Number of Counts to Zero Crossing
Proportional to V
IN
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
TEST17POL3OR
4
B
12
5
B
11
6
B
10
7
B
9
8
B
8
9
B
7
10
B
6
11
B
5
12
B
4
13
B
3
14
2262223242521
STATUS RUN/
HOLD
OSCINOSC
OUT
OSC
SEL
BUFF
OSC
OUT
MODE
To
Analog
Section
COMP OUT
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
High Order
Byte Outputs
Low Order
Byte Outputs
Handshake
Logic
B
2
15
B
1
16
27
SEND
18
19
20
LBEN
HBEN
CE/LOAD
1
GND
14 Latches
12-Bit Counter
14 Three-State Outputs
Latch
Clock
FIGURE 3-1: Conversion Timing (RUN/HOLD) Pin High
FIGURE 3-2: Digital Section
DS21456D-page 10 2002-2012 Microchip Technology Inc.
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