The SY100E417 is a quint LVPECL-to-PECL translator.
It can also be used as a quint PECL-to-LVPECL translator.
The device receives standard PECL signals and translates
them to differential LVPECL output signals (or vice versa).
The SY100E417 can also be used as a differential line
receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.
However, please note that for the latter we will need two
different power supplies. Please refer to Function Table for
more details.
A VBB output is provided for interfacing single ended
input signals. If a single ended input is to be used, the VBB
output should be connected to the Dn input and the active
signal will drive the Dn input. When used, the VBB should
be bypassed to VCC via a 0.01µF capacitor. The VBB is
designed to act as a switching reference for the SY100E417
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100E417 requires three power rails. The VCC and
VCC_VBB supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the VCCO
supply, and GND is connected to the system ground plane.
Both the VCC and VCCO should be bypassed to ground with
a 0.01µF capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100E417 requires three power rails as well. The 5.0V
supply is connected to the VCC and VCCO pins, 3.3V supply
is connected to the VCC_VBB pin and GND is connected to
the system ground plane. VCC_VBB is used to provide a
proper VBB output level if a single ended input is used.
VCC_VBB = 3.3V is only required for single-ended LVPECL
input. For differential LVPECL input, VCC_VBB can be either
3.3V or 5.0V.
Under open input conditions, the Dn input will be biased
at a VCC/2 voltage level and the Dn input will be pulled to
GND. This condition will force the "Qn" output low, ensuring
stability.
Rev.: BAmendment: /1
1
Issue Date: March, 1999
Page 2
Micrel
SY100E417
PIN CONFIGURATION
4
3
4
D
D
D
25 24 23 22 21 20 19
26
D
3
27
D
2
28
D
GND
V
BB
D
D
2
1
2
3
0
4
0
TOP VIEW
PLCC
J28-1
567891011
1
1
D
D
CCO
V
BB
V
CC_
V
0
Q
4
4
CCO
Q
Q
V
18
Q
3
17
Q
3
16
V
CC
15
Q
2
14
Q
2
13
V
CCO
12
Q
1
1
0
Q
Q
CCO
V
PIN NAMES
PinFunction
DnPECL / LVPECL Inputs
QnPECL / LVPECL Outputs
VBBReference Voltage Output
VCCOVCC for Outputs
VCC_VBBVCC for VBB Output
GNDCommon Ground Rail
tPHLD to QS.E.380530680380530680380530680380530680
t
skewWithin-Device Skew
Output-to-Output
Part-to-Part (Diff.)
Duty Cycle (Diff.)
VPPMinimum Input Swing
VCMRCommon Mode Range
(4)
(2)
—20100—20100—20100—20100ps
(2)
—20200—20200—20200—20200
(3)
—25——25——25——25—
150——150——150——150——mV
(5)
V
VPP < 500mV1.3—VCC–0.21.2—VCC–0.21.2—VCC–0.21.2—VCC–0.2
VPP≥ 500mV1.5—VCC–0.21.4—VCC–0.21.4—VCC–0.21.4—VCC–0.2
trOutput Rise/Fall Times Q320—580320—580320—580320—580ps
tf(20% to 80%)
NOTES:
1. Power supply requirements applies as indicated in the DC electrical characteristics tables.
2. Skew is measured between outputs under identical transitions.
3. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device Common Mode Range.
4. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ~40.
5. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V.
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