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PROGRAMMABLE DELAY
CHIP WITH ANALOG INPUT
ClockWorks™
SY10E196
SY100E196
FEATURES
■ Up to 2ns delay range
■ Extended 100E V
EE range of –4.2V to –5.5V
■ ≈20ps digital step resolution
■ Linear input for tighter resolution
■ >1GHz bandwidth
■ On-chip cascade circuitry
■ 75KkΩ input pulldown resistor
■ Fully compatible with Motorola MC10E/100E196
■ Available in 28-pin PLCC package
PIN CONFIGURATION
7
5
3
4
D
D
PLCC
J28-1
EN
SET MIN
6
D
D
NC
SET MAX
CASCADE
CASCADE
18
FTUNE
17
NC
16
V
CC
15
V
CCO
14
Q
13
Q
12
V
CCO
D
D
LEN
V
EE
IN
IN
V
BB
2
D
D
25
24 23 22 21 20 19
26
1
27
0
28
1
2
3
4
TOP VIEW
567891011
NC
NC
DESCRIPTION
The SY10/100E196 are programmable delay chips
(PDCs) designed primarily for very accurate differential
ECL input edge placement applications.
The delay section consists of a chain of gates and a
linear ramp delay adjustment organized as shown in the
logic diagram. The first two delay elements feature gates
that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These
two elements provide the E196 with a digitally-selectable
resolution of approximately 20ps. The required device
delay is selected by the seven address inputs D[0:6],
which are latched on-chip by a high signal on the latch
enable (LEN) control. If the LEN signal is either LOW or
left floating, then the latch is transparent.
The FTUNE input takes an analog coltage and applies
it to an internal linear ramp for reducing the 20s resolution
still further. The FTUNE input is what differentiates the
E196 from the E195.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
PIN NAMES
Pin Function
IN/IN Signal Input
EN Input Enable
D[0:7] Mux Select Inputs
Q/Q Signal Output
LEN Latch Enable
SET MIN Minimum Delay Set
SET MAX Maximum Delay Set
CASCADE Cascade Signal
FTUNE Linear Voltage Input
V
CCO VCC to Output
Rev.: E Amendment: /0
1
Issue Date: October, 1998
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Micrel
ClockWorks™
SY10E196
SY100E196
BLOCK DIAGRAM
EN
IN
SET MAX
SET MIN
LEN
*1.25
1
*1.5
D
0
D
1
D
2
7-Bit Latch
D
3
1
1
1
1
1
1
VBB
IN
1
0
1
0
0
0
*Delays are 25% or 50% longer than
standard (standard = 80ps).
D
4
D
5
D
6
LEN
D
7
D
Latch
Q
Cascade
1
4 gates
1
8 gates
1
16 gates
1
0
0
0
FTUNE
CASCADE
CASCADE
Ramp
Linear
1
0
Q
Q
2
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ClockWorks™
SY10E196
Micrel
SY100E196
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current — — 150 — — 150 — — 150 µA—
EE Power Supply Current mA —
I
10E — 130 156 — 130 156 — 130 156
100E — 130 156 — 130 156 — 150 179
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ClockWorks™
SY10E196
Micrel
SY100E196
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
t
PLH Propagation Delay to Output ps —
PHL IN to Q; Tap = 0 1210 1360 1510 1240 1390 1540 1440 1590 1765
t
IN to Q; Tap = 127 3320 3570 3820 3380 3630 3880 3920 4270 4720
EN to Q; Tap = 0 1250 1450 1650 1275 1475 1675 1350 1650 1950
D7 to CASCADE 300 450 700 300 450 700 300 450 700
RANGE Programmable Range 2000 2175 — 2050 2240 — 2375 2580 — ps —
t
tPD (max.) – tPD (min.)
∆t Step Delay ps 6
0 High — 17 — — 17.5 — — 21 —
D
D1 High — 34 — — 35 — — 42 —
D2 High 55 68 105 55 70 105 65 84 120
D3 High 115 136 180 115 140 180 140 168 205
D4 High 250 272 325 250 280 325 305 336 380
D5 High 505 544 620 515 560 620 620 672 740
D6 High 1000 1088 1190 1030 1120 1220 1240 1344 1450
Lin Linearity D1 D0 —D1 D0 —D1 D0 —— 7
tskew Duty Cycle Skew, tPHL–tPLH — ±30 — — ±30 — — ±30 — ps 1
S Set-up Time ps
t
D to LEN 200 0 — 200 0 — 200 0 —
D to IN 800 — — 800 — — 800 — — 2
EN to IN 200 — — 200 — — 200 — — 3
t
H Hold Time ps
LEN to D 500 250 — 500 250 — 500 250 —
IN to EN 0 — — 0 — — 0 — — 4
R Release Time ps
t
EN to IN 300 — — 300 — — 300 — — 5
SET MAX to LEN 800 — — 800 — — 800 — —
SET MIN to LEN 800 — — 800 — — 800 — —
tjit Jitter — <5 — — <5 — — <5 — ps 8
r Rise/Fall Times ps —
t
tf 20–80% (Q) 125 225 325 125 225 325 125 225 325
20–80% (CASCADE) 300 450 650 300 450 650 300 450 650
NOTES:
1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
2. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set.
3. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75mV to
that IN/IN transition.
4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than
±75mV to that IN/IN transition.
5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified
IN to Q propagation delay and transition times.
6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay
control inputs will typically realize D0 resolution steps across the specified programmable range.
7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing
binary counts on the control inputs Dn). Typically, the device will be monotonic to the D0 input, however, under worst case conditions and process variation,
delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB, the device is guaranteed to be
monotonic over all specified environmental conditions and process variation.
8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
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APPLICATIONS INFORMATION
Analog Input Charateristics: Ftune = VCC to VEE
140
120
100
80
60
40
Propagation Delay (ps)
20
0
–4.5
–3.5 –2.5 –1.5 –0.5
ClockWorks™
SY10E196
SY100E196
Propagation Delay vs Ftune Voltage (100E196)
100
90
80
70
60
50
40
30
Propagation Delay (ps)
20
10
0
–5
–4 –3 –2 –1 –0
Ftune Voltage (V)
Ftune Voltage (V)
Propagation Delay vs Ftune Voltage (10E196)
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SET MAX
SET MIN
Reset
Reset
Reset
Set
Reset
Reset
LEN
LEN
LEN
ClockWorks™
SY10E196
SY100E196
D
0
Bit 0
Q
0
D
1
Bit 1
Q
1
D
2
Bit 2
Q
2
Figure 2. Expansion of the Latch Section of
the E196 Block Diagram
Set
Reset
Set
Reset
Set
Reset
Set
Reset
LEN
LEN
LEN
LEN
LEN
D
3
Bit 3
Q
3
D
4
To Select Multiplexers
Bit 4
Q
4
D
5
Bit 5
Q
5
D
6
Bit 6
Q
6
D
7
Bit 7
Q
7
CASCADE
CASCADE
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Micrel
Using the FTUNE Analog Input
The analog FTUNE pin on the E196 device is intended
to enhance the 20ps resolution capabilities of the fully
digital E195. The level of resolution obtained is
dependent on the number of increments applied to the
appropriate range on the FTUNE pin.
To provide another level of resolution, the FTUNE pin
must be capable of adjusting the delay by greater than
the 20ps digital resolution. As shown in the provided
graphs, this requirement is easily achieved since a 100ps
delay can be achieved over the entire FTUNE voltage
range.This extra analog range ensures that the FTUNE
pin will be capable, even under worst case conditions, of
covering the digital resolution.
ClockWorks™
SY10E196
SY100E196
Typically, the analog input will be driven by an external
DAC to provide a digital control with very fine analog
output steps. The final resolution of the device will be
dependent on the width of the DAC chosen.
To determine the voltage range necessary for the
FTUNE input, the graphs provided should be used. As
an example, if a range of 40ps is selected to cover worst
case conditions and ensure coverage of the digital range,
from the 100E196 graph a voltage range of –3.25V to
–4V would be necessary on the FTUNE pin. Obviously,
there are numerous voltage ranges which can be used
to cover a given delay range. Users are given the
flexibility to determine which one best fits their design.
ADDRESS BUS (A0 – A6)
A
7
6
5
4
D
E196
EN
7
D
D
D
FTUNE FTUNE
VCC
VCCO
Q
Q
VCCO
CASCADE
CASCADE
SET MAX
SET MIN
Figure 1. Cascading Interconnect Architecture
Input
D
1
D
0
LEN
VEE
IN
IN
VBB
2
3
D
D
Chip #1
Cascading Multiple E196s
To increase the programmable range of the E196,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple E196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple PDCs will result in a larger
programmable range; however, this increase is at the
expense of a longer minimum delay.
Figure 1 illustrates the interconnect scheme for
cascading two E196s. As can be seen, this scheme can
easily be expanded for larger E196 chains. The D7 input
of the E196 is the cascade control pin. With the
interconnect scheme of Figure 1, when D7 is asserted, it
signals the need for a larger programmable range than
is achievable with a single device.
LINEAR
INPUT
D
1
D
0
LEN
VEE
IN
IN
VBB
4
3
2
D
D
D
E196
Chip #2
EN
6
5
D
D
SET MIN
SET MAX
7
D
VCC
VCCO
VCCO
CASCADE
CASCADE
Q
Q
Output
An expansion of the latch section of the block diagram
is pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When
D7 of chip #1 above is low, the cascade output will also
be low, while the cascade bar output will be a logical
high. In this condition, the SET MIN pin of chip #2 will
be asserted and, thus, all of the latches of chip #2 will
be reset and the device will be set at its minimum delay.
Since the RESET and SET inputs of the latches are
overriding, any changes on the A0–A6 address bus will
not affect the operation of chip #2.
Chip #1, on the other hand, will have both SET MIN
and SET MAX de-asserted so that its delay will be
controlled entirely by the address bus A0–A6. If the delay
needed is greater than can be achieved with 31.75 gate
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delays (1111111 on the A0–A6 address bus), D7 will be
asserted to signal the need to cascade the delay to the
next E196 device. When D7 is asserted, the SET MIN
pin of chip #2 will be de-asserted and the delay will be
controlled by the A0–A6 address bus. Chip #1, on the
other hand, will have its SET MAX pin asserted, resulting
in the device delay to be independent of the A
0–A6
address bus.
When the SET MAX pin of chip #1 is asserted, the D0
and D1 latches will be reset, while the rest of the latches
will be set. In addition, to maintain monotonicity, an
additional gate delay is selected in the cascade circuitry.
As a result, when D7 of chip #1 is asserted, the delay
increases from 31.75 gates to 32 gates. A 32-gate delay
is the maximum delay setting for the E196.
When cascading multiple PDCs, it will prove more costeffective to use a single E196 for the MSB of the chain,
while using E195 for the lower order bits. This is due to
the fact that only one fine tune input is needed to further
reduce the delay step resolution.
ClockWorks™
SY10E196
SY100E196
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E196JC J28-1 Commercial
SY10E196JCTR J28-1 Commercial
SY100E196JC J28-1 Commercial
SY100E196JCTR J28-1 Commercial
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Micrel
28 LEAD PLCC (J28-1)
ClockWorks™
SY10E196
SY100E196
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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