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8-BIT SYNCHRONOUS
BINARY UP COUNTER
SY10E016
SY100E016
FEATURES
■ 700MHz min. count frequency
■ Extended 100E VEE range of –4.2V to –5.5V
■ 1000ps CLK to Q, TC
■ Internal, gated TC feedback
■ 8 bits wide
■ Fully synchronous counting and TC generation
■ Asynchronous Master Reset
■ Fully compatible with industry standard 10KH,
100K I/O levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E016
■ Available in 28-pin PLCC package
PIN CONFIGURATION
6
VCCO
TC
P5
18
Q7
17
Q6
16
VCC
Q5
15
14
VCCO
13
Q4
12
Q3
MR
CLK
TCLD
VEE
NC
P
P1
CE
PE
P7
P
25 24 23 22 21 20 19
26
27
28
1
2
0
3
4
567891011
PLCC
TOP VIEW
J28-1
DESCRIPTION
The SY10/100E016 are high-speed synchronous,
presettable and cascadable 8-bit binary counters designed
for use in new, high-performance ECL systems. Architecture
and operation are the same as the Motorola MC10H016 in
the MECL 10KH family, extended to 8 bits, as shown in the
logic diagram.
The counters feature internal feedback of TC, gated by
the TCLD (terminal count load) pin. When TCLD is LOW,
the TC feedback is disabled and counting proceeds
continuously, with TC going LOW to indicate an all-HlGH
state. When TCLD is HIGH, the TC feedback causes the
counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter.
PIN NAMES
Pin Function
P0-P7 Parallel Data (Preset) Inputs
Q0-Q7 Data outputs
CE Count Enable Control Input
PE Parallel Load Enable Control Input
MR Master Reset
CLK Clock
TC Terminal Count Output
TCLD TC-Load Control Input
V
CCO VCC to Output
P4
P2
P3
VCCO
Q2
Q1
Q0
Rev.: D Amendment: /2
1
Issue Date: May, 1998
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BLOCK DIAGRAM
Q
SY10E016
SY100E016
TC
7
BIT 7
P
7
CE
Q
0Q1Q2Q3Q4Q5Q6
Q2 – Q
Q
Q
6
5
5
BIT 2 – BIT 6
5
5
5
1
5
BIT 1
P
1
CE
0
Q
0
SLAVE
Q0M
Q0M
MASTER
BIT 0
PE
TCLD MR CLK
CE
P
0
2
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SY10E016
SY100E016
TRUTH TABLE
(1)
CE PE TCLD MR CLK Function
X L X L Z Load Parallel (Pn to Qn)
L H L L Z Continuous Count
L H H L Z Count; Load Parallel on TC = LOW
H H X L Z Hold
X X X L ZZ Master respond, Slaves Hold
X X X H Z Reset (Q
NOTE:
1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW)
n : = LOW, TC : = HIGH)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
IIH Input HIGH Current — — 150 — — 150 — — 150 — — 150 µA
I
EE Power Supply Current mA
10E — 151 181 — 151 181 — 151 181 — 151 181
100E — 151 181 — 151 181 — 151 181 — 174 208
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CTA = 0°CTA = 25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
fCOUNT Max. Count Frequency 700 900 — 700 900 — 700 900 — 700 900 — MHz
PLH Propagation Delay to Output ps
t
tPHL CLK to Q 600 725 1000 600 725 1000 600 725 1000 600 725 1000
MR to Q 600 775 1000 600 775 1000 600 775 1000 600 775 1000
CLK to TC (Qs loaded)
CLK to TC (Qs unloaded)
MR to TC 625 775 1000 625 775 1000 625 775 1000 625 775 1000
t
S Set-up Time ps
Pn 150 –30 — 150 –30 — 150 –30 — 150 –30 —
CE 600 400 — 600 400 — 600 400 — 600 400 —
PE 600 400 — 600 400 — 600 400 — 600 400 —
TCLD 500 300 — 500 300 — 500 300 — 500 300 —
H Hold Time ps
t
Pn 250 30 — 250 30 — 250 30 — 250 30 —
CE 0 –400 — 0 –400 — 0 –400 — 0 –400 —
PE 0 –400 — 0 –400 — 0 –400 — 0 –400 —
TCLD 100 –300 — 100 –300 — 100 –300 — 100 –300 —
tRR Reset Recovery Time 900 700 — 900 700 — 900 700 — 900 700 — ps
WP Minimum Pulse Width 400 — — 400 — — 400 — — 400 — — ps
t
CLK, MR
r Rise/Fall Times 300 510 800 300 510 800 300 510 800 300 510 800 ps
t
tf 20% to 80%
NOTE:
1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII
state to a 0000 0000 state causes the CLk to TC+ delay to increase.
(1)
550 775 1050 550 775 1050 550 775 1050 550 775 1050
(1)
550 700 900 550 700 900 550 700 900 550 700 900
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SY10E016
Micrel
SY100E016
FUNCTION TABLE
Function PE CE MR TCLD CLK P7–P4 P3 P2 P1 P0 Q7–Q4 Q3 Q2 Q1 Q0 TC
Load L X L X Z H H H L L H H H L L H
Count H L L L Z XXXXXHHHLHH
HLLLZ XXXXXHHHHLH
HLLLZ XXXXXHHHHHL
HLLLZ XXXXXLLLLLH
Load L X L X Z H H H L L H H H L L H
Hold HHLXZ XXXXXHHHLLH
HHLXZ XXXXXHHHLLH
Load On H L L H Z H L H H L H H H L H H
Terminal H L L H Z H L H H L HHHHLH
Count H L L H Z H L H H L HHHHHL
HLLHZ HLHHLHLHHLH
HLLHZ HLHHLHLHHHH
HLLHZ HLHHLHHLLLH
Reset X X H X X XXXXXLLLLLH
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APPLICATIONS INFORMATION
SY10E016
SY100E016
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output and
count enable input (CE) greatly facilitate the cascading of
E016 devices. Two E016s can be cascaded without the need
for external gating; however, for counters wider than 16 bits,
external OR gates are necessary for cascade implementations.
Figure 1, below, pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the E101
gates used to OR the terminal count outputs of the lower order
E016s to control the counting operation of the higher order
bits. When the terminal count of the preceding device (or
devices) goes low (the counter reaches an all 1s state), the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition. In
addition, the preceding devices will also count one bit, thus
sending their terminal count outputs back to a high state,
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
LOAD
E016 in the chain to count all of the lower order terminal count
outputs, it must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or subtracting
E016 devices from Figure 1 and maintaining the logic pattern
illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary set-up time of the CE input and the
propagation delay through the OR gate controlling it (for 16bit counters the limitation is only the TC propagation delay and
the CE set-up time). Figure 1 shows E101 gates used to
control the count enable inputs; however, if the frequency of
operation is lower, a slower ECL OR gate can be used. Using
the worst case guarantees for these parameters from the
ECLinPS data book, the maximum count frequency for a
greater than 16-bit counter is 475MHz and that for a 16-bit
counter is 625MHz. Note that this assumes the trace delay
between the TC outputs and the CE inputs are negligible. If
this is not the case, estimates of these delays need to be
added to the calculations.
"LO"
CLOCK
Q0–Q
7
CE PE
E016
LSB
P0–P
TC
7
CLK
Q0–Q
7
CE PE CE PE CE PE
E016
TCCLK
P0–P
7
Figure 1. 32-Bit Cascaded E016 Counter
E101
Q0–Q
E016
P0–P
7
TCCLK
7
E101
Q0–Q
E016
MSB
P0–P
7
TCCLK
7
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SY10E016
SY100E016
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count), when asserted, reloads the
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 2
below illustrates the input conditions necessary for utilizing
the E016 as a programmable divider set up to divide by 113.
HLL HHLHH
7P6P5P4P3P2P1P0
P
H
PE
L
CE
H
TCLD
CLK
7Q6Q5Q4Q3Q2Q1Q0
Q
To determine what value to load into the device to accomplish
the desired division, the designer simply subtracts the binary
equivalent of the desired divide ratio for the binary value for
256. As an example for a divide ration of 113:
PN's = 256 – 113 = 8F
16 = 1000 1111
where
P0 = LSB and P7 = MSB
Forcing this input condition, as per the set-up in Figure 2, will
result in the waveforms of Figure 3. Note that the TC output
TC
CLOCK
PE
TC
Figure 2. Mod 2 to 256 Programmable Divider
LOAD 1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111 LOAD
Divide by 113
Figure 3. Divide by 113 E016 Programmable Divider Waveforms
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Divide Preset Data Inputs
Ratio P7 P6 P5 P4 P3 P2 P1 P0
2HHHHHHHL
3 H H HHH H L H
4 H H HHH H L L
5 H H HHH L H H
•••••• • ••
•••••• • ••
112 H L L H L L L L
113 H L L L H H H H
114 H L L L H H H L
•••••• • ••
•••••• • ••
254 L L L L L L H L
255 L L L L L L L H
256 L L L L L L L L
Table 1. Preset Values for Various Divide Ratios
SY10E016
SY100E016
is used as the divide output and the pulse duration is equal to
a full clock period. For even divide ratios twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip-flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256, inclusive. If divide ratios of greater than 256 are needed,
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers, the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
Figure 4 on the following page shows a typical block
diagram of a 32-bit divider chain. Once again, the maximize
the frequency of operation, E101 OR gates were used. For
lower frequency applications, a slower OR gate could replace
the E101. Note that for a 16-bit divider, the OR function
feeding the PE (program enable) input CANNOT be replaced
by a wire OR tie as the TC output of the least significant E016
must also feed the CE input of the most significant E016. If the
two TC outputs were OR tied, the cascaded count operation
would not operate properly. Because in the cascaded form
the PE feedback is external and requires external gating, the
maximum frequency of operation will be significantly less than
the same operation in a single device.
Maximizing E016 Count Frequency
The E016 device produces nine fast transitioning singleended outputs; thus, VCC noise can become significant in
situations where all of the outputs switch simultaneously in the
same direction. This VCC noise can negatively impact the
maximum frequency of operation of the device. Since the
device does not need to have the Q outputs terminated to
count properly, it is recommended that, if the outputs are not
going to be used in the rest of the system, they should be left
unterminated. In addition, if only a subset of the Q outputs are
used in the system, only those outputs should be terminated.
Not terminating the unused outputs will not only cut down the
VCC noise generated, but will also save in total system power
dissipation. Following these guidelines will allow designers to
either be more aggressive in their designs, or provide them
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Q0–Q
SY10E016
SY100E016
E101
Q0–Q
7
7
Q0–Q
7
Q0–Q
7
"LO"
CLOCK
CE PE
E016
LSB
CLK
P0–P
TC
7
CE PE CE PE CE PE
E016
E016
E016
MSB
CLK
Figure 4. 32-Bit Cascaded E016 Programmable Divider
P0–P
TC
7
E101 E101
CLK
P0–P
TC
7
CLK
P0–P
TC
7
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E016JC J28-1 Commercial
SY10E016JCTR J28-1 Commercial
SY100E016JC J28-1 Commercial
SY100E016JCTR J28-1 Commercial
Ordering Package Operating
Code Type Range
SY10E016JI J28-1 Industiral
SY10E016JITR J28-1 Industrial
SY100E016JI J28-1 Industrial
SY100E016JITR J28-1 Industrial
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28 LEAD PLCC (J28-1)
SY10E016
SY100E016
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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