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STY100NS20FD
N-CHANNEL 200V - 0.022Ω - 100A Ma x24 7
MESH OVERLAY™ Power MOSFET
TYPE V
DSS
R
DS(on)
I
D
STY100NS20FD 200V < 0.024Ω 100 A
n
TYPICAL RDS(on) = 0.022Ω
n
EXTREMELY HIGH dv /d t C APABILITY
n
100% AVALANCHE TESTED
n
GATE CHARGE MINIMIZED
n
± 20V GATE TO SOURCE VOLTAGE RATING
n
LOW INTRINSIC CAPACITANCE
n
FAST BODY-DRAIN DIODE:LOW trr, Q
rr
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding
performances. The new patented S Trip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(ON) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteristics.
APPLICATIONS
n
HIGH CURRENT, HIGH SPEED SWITCHING
n
SWITCH MODE POWER SUPPLY (SM PS)
n
DC-AC CONVERTER FOR WELDING
EQUIPMENT AND UNINTERRUPTABLE
POWER SUPPLY AND MOTOR DRIVE
3
2
1
Max247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt (1) Peak Diode Recovery voltage slope 25 V/ns
T
stg
T
j
(•)Pu l se width limited by safe operati ng area
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
200 V
200 V
Gate- source Voltage ±20 V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
(l)
Drain Current (pulsed) 400 A
Total Dissipation at TC = 25°C
100 A
63 A
450 W
Derating Factor 3.6 W/°C
Storage Temperature –65 to 150 °C
Max. Operating Junction Temperature 150 °C
(1)ISD ≤100A, di/dt ≤200A/µs, VDD ≤ V
(BR)DSS
, Tj ≤ T
JMAX
1/8January 2002
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STY100NS20FD
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.277 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
Drain-source
= 25 °C, ID = IAR, VDD = 50 V)
j
ID = 250 µA, VGS = 0 200 V
100 A
750 mJ
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
V
= Max Rating
DS
VDS = Max Rating, TC = 125 °C
V
= ± 20V ±100 nA
GS
10 µA
100 µA
ON
(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
V
= VGS, ID = 250µA
DS
VGS = 10V, ID = 50A
345V
0.022 0.024 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 1500 pF
Reverse Transfer
I
D
V
Capacitance
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 %.
= 50A
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
30 S
7900 pF
460 pF
2/8
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STY100NS20FD
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 140 ns
Total Gate Charge
Gate-Source Charge 35 nC
Gate-Drain Charge 135 nC
SWITCHING OFF
Symbol Param eter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
t
f
c
Off-voltage Rise Time
Fall Time 140 ns
Cross-over Time 220 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limi ted by safe operating area.
(2)
Source-drain Current 100 A
Source-drain Current (pulsed) 400 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charg e 1.35 µ C
Reverse Recovery Curren t 12 A
= 100V, ID = 50A
DD
RG= 4.7Ω VGS = 10V
(see test circuit, Figure 3)
V
= 100V, ID = 100A,
DD
V
= 10V
GS
V
= 100V, ID = 100A,
DD
RG= 4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
ISD = 100A, VGS = 0
I
= 100A, di/dt = 100A/µs,
SD
V
= 160V, Tj = 150°C
DD
(see test circuit, Figure 5)
42 ns
360 nC
245 ns
1.6 V
225 ns
Safe Operating Area Thermal Impedance
3/8
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STY100NS20FD
Transfer CharacteristicsOutput Characteristics
Transconductance
Gate Charge vs Gate-source Voltage
Static Drain-source On Resistance
Capacitance Variations
4/8
Page 5
Source-drain Diode Forw ard Ch aracteristi cs
STY100NS20FD
Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.
5/8
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STY100NS20FD
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
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Max247 MECHANICAL DATA
STY100NS20FD
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.70 5.30
A1 2.20 2.60
b 1.00 1.40
b1 2.00 2.40
b2 3.00 3.40
c 0.40 0.80
D 19.70 20.30
e 5.35 5.55
E 15.30 15.90
L 14.20 15.20
L1 3.70 4.30
mm inch
P025Q
7/8
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STY100NS20FD
8/8
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of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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