Datasheet STW81102 Datasheet (ST)

Multi-band RF frequency synthesizer with integrated VCOs

Features

■ Integer-N frequency synthesizer

■ Dual differential integrated VCOs with

automatic center frequency calibration:
– 3000 - 3620 MHz (direct output)
– 4000 - 4650 MHz (direct output)
– 1500 - 1810 MHz (internal divider by 2)
– 2000 - 2325 MHz (internal divider by 2)
– 750 - 905 MHz (internal divider by 4)
– 1000 - 1162.5 MHz (internal divider by 4)

■ Excellent integrated phase noise

■ Fast lock time: 150 µs

■ Dual modulus programmable prescaler (16/17

or 19/20)

■ 2 programmable counters to achieve a

feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).

■ Programmable reference frequency divider (10

bits)

■ Phase frequency comparator and charge pump

■ Programmable charge pump current

■ Digital lock detector

■ Dual digital bus Interface: SPI and I

3 bit programmable address (1100A

■ 3.3V power supply

■ Power down mode (HW and SW)

■ Small size exposed pad VFQFPN28 package

5x5x1.0mm

■ Process: BICMOS 0.35 µm SiGe

2

C bus with

)

2A1A0

STW81102

Applications

■ 2.5G and 3G cellular infrastructure equipment

■ CATV equipment

■ Instrumentation and test equipment

■ Other wireless communication systems

Description

The STMicroelectronics STW81102 is an
integrated RF synthesizer with voltage controlled
oscillators (VCOs). Showing high performance,
high integration, low power, and multi-band
performances, the STW81102 is a low-cost one­chip alternative to discrete PLL and VCOs
solutions.

The STW81102 includes an Integer-N frequency
synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
noise floor of -155 dBc/Hz.

The combination of wide frequency range VCOs
(using center-frequency calibration over 32 sub­bands) and multiple output options (direct output,
divided by 2 or divided by 4) allows coverage from
750 MHz to 905 MHz and 1000MHz to 1162.5
MHz, from 1500MHz to 1810 MHz and 2000 MHz
to 2325MHz, from 3000 MHz to 3620 MHz and
4000MHz to 4650 MHz bands.

The STW81102 is designed with
STMicroelectronics advanced 0.35µm SiGe
process.

January 2008 Rev 5 1/53

www.st.com

1

Contents STW81102

Contents

1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.8 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.8.1 VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.8.2 VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.8.3 VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.9 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.9.1 Output Buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.10 External VCO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6I

2/53

2

C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

STW81102 Contents

6.1.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.2 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.3 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.4 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.5 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.6 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.7 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2

6.3 I

C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.2 Read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.3 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.3 Bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1 Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.2 Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.3 Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.4 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3/53

List of tables STW81102

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Operating conditions (refer to

Table 4. Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. VCO A performances versus amplitude setting (freq=3.3GHz) . . . . . . . . . . . . . . . . . . . . . 24

Table 9. VCO B performances versus amplitude setting (freq=4.3GHz) . . . . . . . . . . . . . . . . . . . . . 25

Table 10. EXT_PD pin function setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11. Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 12. Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13. Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 14. Data and clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 15. Start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. Ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17. Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18. Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 21. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22. Bits at 00h and ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. Bits at 01h and ST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 25. Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 26. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 36: Typical application diagram

) . . . . . . . . . . . . . . . . 9

4/53

STW81102 List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. VCO A (direct output) closed loop phase noise at 3.6GHz
(F
Figure 6. VCO B (direct output) closed loop phase noise at 4.3GHz
(F
Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.65GHz
(F
Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.15GHz
(F
Figure 9. VCO A (div. by 4 output) closed loop phase noise at 825MHz
(F
Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1.075GHz
(F
Figure 11. PFD frequency spurs (direct output; F
Figure 12. PFD frequency spurs (div. by 2 output; F
Figure 13. PFD frequency spurs (div. by 4 output; F
Figure 14. Settling time (final frequency=2.15 GHz; F

Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41

Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42

Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43

Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43

Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44

Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44

Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45

Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46

Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 38. Application diagram with external VCO (LO output from STW81102) . . . . . . . . . . . . . . . . 49

Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49

Figure 40. VFQFPN28 mechanical drawing (

=200kHz; F

STEP

=200kHz; F

STEP

=200kHz; F

STEP

=200kHz; F

STEP

=200kHz; F

STEP

=200kHz; F

STEP

=200kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PFD

=200kHz; ICP=4mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PFD

=400kHz; ICP=2mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PFD

=400kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PFD

=800kHz; ICP=1.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PFD

=800kHz; ICP=2.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PFD

Note 1

=200kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PFD

=400kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PFD

=800kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PFD

=400kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . 17

PFD

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5/53

Block diagram and pin configuration STW81102

1 Block diagram and pin configuration

1.1 Block diagram

Figure 1. Block diagram

VDD_OUTBUF

VSS_OUTBUF

DI V4

EXT
VCO
BUF

BUF

DIV4

VDD_DIV4
VSS_DIV4

VDD_DIV2
VSS_DIV2

VDD_BUFVCO
VSS_BUFVCO

EXTVCO_INP

EXTVCO_INN

VDD_VCOA

VSS_VCOA

VDD_VCOB

VSS_VCOB

VDD_ESD

VSS_ESD

OUTB UFP

BUF

VCO

BUFF

VCTRL

OUTB UFN

REF_CLK

VDD_PLL

VSS_PLL

REXT

BUF

VCO

BUF

BUF

DIV 2

DIV2

REF

Divider

VCO

Divider

VSS_CP
VDD_CP

P

UP

F
D

C

ICP

P

DN

LOCK_DET

DBUS _SEL

SCL / CLK

DBUS

SDA / DATA

ADD0 / LOAD
ADD1
ADD2

VCO

Calibrator

VDD_DBUS
VSS_DBUS

TEST1

TEST2

EXT_PD

6/53

STW81102 Block diagram and pin configuration

1.2 Pin configuration

Figure 2. Pin connection (top view)

ADD2

ADD1

ADD0/LOAD

SCL/CLK

SDA/DATA

EXT_PD

VDD_DBUS

VDD_VCOA

VDD_DIV2

VDD_OUTBUF

OUTBUFP

OUTBUFN

VDD_DIV4

VDD_VCOB

DBUS_SEL

VDD_BUFVCO

EXTVCO_INP

VFQFPN28

QFN 28

EXTVCO_INN

VDD_PLL

REF_CLK

TEST2

ICP

VCTRL

VDD_ESD

REXT

TEST1

VDD_CP

LOCK_DET

Table 1. Pin description

Pin No Name Description Observation

1 VDD_VCOA VCOA power supply

2 VDD_DIV2 Divider by 2 power supply

3 VDD_OUTBUF Output buffer power supply

4 OUTBUFP LO buffer positive output Open collector

5 OUTBUFN LO buffer negative output Open collector

6 VDD_DIV4 Divider by 4 power supply

7 VDD_VCOB VCOB power supply

8 VDD_ESD ESD positive rail power supply

9 VCTRL VCO control voltage

10 ICP PLL charge pump output

7/53

Block diagram and pin configuration STW81102

Table 1. Pin description (continued)

Pin No Name Description Observation

11 REXT

External resistance connection for
PLL charge pump

12 VDD_CP Power supply for charge pump

For test purposes only;

13 TEST1 Test input 1

must be connected to
GND

14 LOCK_DET Lock detector

CMOS output

= 4 mA)

(I

OUT

For test purposes only;

15 TEST2 Test input 2

must be connected to
GND

16 REF_CLK Reference clock input

17 VDD_PLL PLL digital power supply

For test purposes only;

18 EXTVCO_INN External VCO negative input

must be connected to
GND

For test purposes only;

19 EXTVCO_INP External VCO positive input

must be connected to
GND

20 VDD_BUFVCO VCO buffer power supply

21 DBUS_SEL Digital bus interface select CMOS input

2

22 VDD_DBUS SPI and I

C bus power supply

23 EXT_PD

Power down hardware
‘0’ device ON; ‘1’ device OFF

24 SDA/DATA I2CBUS/SPI data line

25 SCL/CLK I2CBUS/SPI clock line

26 ADD0/LOAD

I2CBUS address select pin/ SPI load
line

27 ADD1 I2CBUS address select pin

28 ADD2 I2CBUS address select pin

CMOS input

CMOS Bidir Schmitt
triggered (I

OUT

=4 mA)

CMOS input
Schmitt triggered

CMOS input

CMOS input; must be
connected to GND in
SPI mode

CMOS input; must be
connected to GND in
SPI mode

8/53

STW81102 Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Values Unit

AV

Analog supply voltage 0 to 4.6 V

CC

DVCC Digital supply voltage 0 to 4.6 V

T

stg

Storage temperature -65 to 150 °C

Electrical static discharge

(1)

ESD

- HBM

- CDM-JEDEC standard

- MM

1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800V.

4

1.5

0.2

2.2 Operating conditions

Table 3. Operating conditions (refer to

Symbol Parameter Test conditions Min Typ Max Unit

AV

DD

DV

DD

I

VDD1

I

VDD2

T

amb

T

j

Figure 36: Typical application diagram

)

Analog supply voltage 3.0 3.3 3.6 V

Digital supply voltage 3.0 3.3 3.6 V

V

current consumption 90 mA

DD1

V

current consumption 12 mA

DD2

Operating ambient
temperature

Maximum junction
temperature

-40 85 °C

125 °C

kV

R

th j-amb

R

th j-b

R

th j-c

Junction to ambient package
thermal resistance

Junction to board package
thermal resistance

Junction to case package
thermal resistance

Multilayer JEDEC board 35 °C/W

Multilayer JEDEC board 26.3 °C/W

Multilayer JEDEC board 6.3 °C/W

9/53

Electrical specifications STW81102

2.3 Digital logic levels

Table 4. Digital logic levels

Symbol Parameter Test conditions Min Typ Max Unit

V

V

V

hyst

V

V

Low level input voltage 0.2*Vdd V

il

High level input voltage 0.8*Vdd V

ih

Schmitt trigger hysteresis 0.8 V

Low level output voltage 0.4 V

ol

High level output voltage 0.85*Vdd V

oh

2.4 Electrical specifications

All the electrical specifications are intended at 3.3V supply voltage.

Table 5. Electrical specifications

Symbol Parameter Test conditions Min Typ Max Unit

Output frequency range

F

OUTA

F

OUTB

Output frequency range with
VCOA

Output frequency range with
VCOB

Direct output 3000 3620 MHz

Divider by 2 1500 1810 MHz

Divider by 4 750 905 MHz

Direct output 4000 4650 MHz

Divider by 2 2000 2325 MHz

Divider by 4 1000 1162.5 MHz

VCO dividers

N VCO divider ratio

Prescaler 16/17 256 65551

Prescaler 19/20 361 77836

Reference clock and phase frequency detector

F

Reference input frequency 10 200 MHz

ref

Reference input sensitivity

(1)

0.35 1 1.5 Vpeak

R Reference divider ratio 2 1023

F

F

PFD

STEP

PFD input frequency 16 MHz

/

F

OUT

65551

F

OUT

77836

/

Frequency step

(2)

Prescaler 16/17

Prescaler 19/20

Charge pump

(3)

3bit programmable 5 mA

0.4 V

V

I

CP

OCP

ICP sink/source

Output voltage compliance
range

10/53

F

/

OUT

256

F

/

OUT

361

-0.3 V

dd

Hz

Hz

STW81102 Electrical specifications

Table 5. Electrical specifications (continued)

Symbol Parameter Test conditions Min Typ Max Unit

Spurious

VCOs

K

K

VCOA

VCOB

VCOA sensitivity

VCOB sensitivity

Maximum temperature

ΔΤ

variation for continuous

LK

lock

VCO A pushing

VCO B pushing

V

CTRL

VCO control voltage

LO harmonic spurious

I

VCOA

I

VCOB

I

VCOBUF

I

DIV2

I

DIV4

VCOA current consumption

VCOB current consumption

VCO buffer consumption 15 mA

Divider by 2 consumption 17 mA

Divider by 4 consumption 13 mA

LO output buffer

(5)(6)

(4)

(5)

(5)

(5)

(5)

Direct output
(F

= 200 kHz)

PFD

Divider by 2
(F

= 400 kHz)

PFD

Divider by 4

= 800 kHz)

(F

PFD

-73 dBc

-83 dBc

-91 dBc

Lower frequency range 40 55 70 MHz/V

Intermediate frequency range 60 75 95 MHz/V

Higher frequency range 80 105 140 MHz/V

Lower frequency range 30 45 60 MHz/V

Intermediate frequency range 40 55 70 MHz/V

Higher frequency range 50 70 90 MHz/V

VCO A 115

° C

VCO B 95

47MHz/V

14 20 MHz/V

(5)

(5)

F

=3.3GHz; amplitude [11] 30 mA

VCO

F

=3.3GHz; amplitude [00] 16 mA

VCO

F

=4.3GHz; amplitude [11] 22 mA

VCO

F

=4.3GHz; amplitude [00] 11 mA

VCO

0.4 3 V

-20 dBc

P

LO

R

L

I

OUTBUF

Output level 0 dBm

Return loss

(5)

Matched to 50 ohms 15 dB

DIV4 buff 27 mA

Current consumption

DIV2 buff 23 mA

Direct output 39 mA

=4GHz) 43

OUT

62

67

dB

Output buffer isolation (power
down state)

Direct output (F

Divider by 2 output

=2GHz)

(F

OUT

Divider by 4 output

=1GHz)

(F

OUT

11/53

Electrical specifications STW81102

Table 5. Electrical specifications (continued)

Symbol Parameter Test conditions Min Typ Max Unit

External VCO

Frequency range 0.625 5 GHz

Input level -10 +6 dBm

Current consumption VCO internal buffer 28 mA

PLL miscellaneous

I

PLL

t

lock

1. In order to achieve best phase noise performance 1V peak level is suggested.

2. The frequency step is related to the PFD input frequency as follows:

- F

- F

- F

3. See relationship between ICP and REXT in

4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
BW.

5. Guaranteed by design and characterization.

6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range
for the VCO covering the desired frequency. Once programmed at the initial temperature T
temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status only if the temperature drift (in
either direction) is within the limit specified by
If higher ΔT are required the ”
calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal)

7. Frequency jump from 2300 to 2150 MHz; it includes the time required by the VCO calibration procedure (7 F
F

PFD

Current consumption

Lock up time

= F

STEP
STEP
STEP

=400kHz).

for direct output

PFD

= F

/2 for divided by 2 output

PFD

= F

/4 for divided by 4 output

PFD

(5), (7)

VCO calibration auto-restart

Input buffer, prescaler, digital
dividers, misc.

25kHz PLL bandwidth; within
1 ppm of frequency error

Section 5.7: Charge pump

ΔT

, provided that the final temperature T1 is still inside the nominal range.

LK

“ feature can be enabled, thus allowing to re-start the VCO

.

12 mA

150 µs

inside the operating

0

cycles with

PFD

12/53

STW81102 Electrical specifications

2.5 Phase noise specification

Table 6. Phase noise specification

Parameter Test conditions Min Typ Max Unit

Phase noise performance

Inband phase noise floor – closed loop

Normalized inband phase noise
floor

(1)

(2)

ICP=4mA, PLL BW = 50kHz;
including reference clock
contribution

Inband phase noise floor
direct output

Inband phase noise floor
divider by 2

ICP=4mA, PLL BW = 50kHz;
including reference clock

contribution

Inband phase noise floor
divider by 4

PLL integrated phase noise – direct output

= 4.3 GHz,

F

Integrated phase noise
100 Hz to 40 MHz

OUT

F

= 200kHz, F

PFD

PLL BW = 15kHz, ICP=4mA

PLL integrated phase noise – divider by 2

= 2.15 GHz,

F

Integrated phase noise
100Hz to 40MHz

OUT

F

= 400kHz, F

PFD

PLL BW = 20kHz, ICP=3mA

STEP

STEP

=200 kHz,

=200 kHz,

-222 dBc/Hz

-222+20log(N)+10log(

-228+20log(N)+10log(F

-234+20log(N)+10log(F

-35 dBc

1.4 ° rms

-44 dBc

0.52 ° rms

F

)dBc/Hz

PFD

)dBc/Hz

PFD

)dBc/Hz

PFD

PLL integrated phase noise – divider by 4

F

= 1.075 GHz,

Integrated phase noise
100Hz to 40MHz

OUT

F

= 800kHz, F

PFD

PLL BW = 30kHz, ICP=2.5mA

VCO A direct (3000MHz-3620MHz) – open loop

(3)

STEP

=200 kHz,

-51 dBc

0.22 ° rms

Phase noise @ 1 kHz -57 dBc/Hz

Phase noise @ 10 kHz -84 dBc/Hz

Phase noise @ 100 kHz -107 dBc/Hz

Phase noise @ 1 MHz -129 dBc/Hz

Phase noise @ 10 MHz -149 dBc/Hz

Phase noise @ 40 MHz -159 dBc/Hz

VCO B direct (4000MHz-4650MHz) – open loop

(3)

Phase noise @ 1 kHz -55 dBc/Hz

Phase noise @ 10 kHz -83 dBc/Hz

Phase noise @ 100 kHz -106 dBc/Hz

Phase noise @ 1 MHz -128 dBc/Hz

Phase noise @ 10 MHz -148 dBc/Hz

Phase noise @ 40 MHz -158 dBc/Hz

13/53

Electrical specifications STW81102

Table 6. Phase noise specification (continued)

Parameter Test conditions Min Typ Max Unit

VCO A with divider by 2 (1500MHz-1810MHz) – open loop

Phase noise @ 1 kHz -63 dBc/Hz

Phase noise @ 10 kHz -90 dBc/Hz

Phase noise @ 100 kHz -113 dBc/Hz

Phase noise @ 1 MHz -135 dBc/Hz

Phase noise @ 10 MHz -151.5 dBc/Hz

Phase noise floor @ 40 MHz -155 dBc/Hz

VCO B with divider by 2 (2000MHz-2325MHz) – open loop

Phase noise @ 1 kHz -61 dBc/Hz

Phase noise @ 10 kHz -89 dBc/Hz

Phase noise @ 100 kHz -112 dBc/Hz

Phase noise @ 1 MHz -134 dBc/Hz

Phase noise @ 10 MHz -151.5 dBc/Hz

Phase noise floor @ 40 MHz -155 dBc/Hz

VCO A with divider by 4 (750MHz-905MHz) – open loop

(3)

(3)

(3)

Phase noise @ 1 kHz -69 dBc/Hz

Phase noise @ 10 kHz -96 dBc/Hz

Phase noise @ 100 kHz -119 dBc/Hz

Phase noise @ 1 MHz -141 dBc/Hz

Phase noise @ 10 MHz -154 dBc/Hz

Phase noise floor @ 40 MHz -155 dBc/Hz

VCO B with divider by 4 (1000MHz-1162.5MHz) – open loop

(3)

Phase noise @ 1 kHz -67 dBc/Hz

Phase noise @ 10 kHz -95 dBc/Hz

Phase noise @ 100 kHz -118 dBc/Hz

Phase noise @ 1 MHz -140 dBc/Hz

Phase noise @ 10 MHz -154 dBc/Hz

Phase noise floor @ 40 MHz -155 dBc/Hz

1. Phase noise SSB.
VCO amplitude setting to value [11].
All the closed-loop performances are specified using a reference clock signal at 76.8 MHz with phase noise of

-135dBc/Hz @1kHz offset, -145 dBc/Hz @10 kHz offset and -149.5dBc/Hz of noise floor.

2. Normalized PN = Measured PN – 20log(N) – 10log(F
comparison frequency at the PFD input.

3. Typical phase noise at centre band frequency.

) where N is the VCO divider ratio (N=B*P+A) and F

PFD

PFD

is the

An evaluation kit is available upon request, including a powerful simulation tool
(STWPLLSim) that allows a very accurate estimation of the device’s phase noise according
to the desired project parameters (VCO frequency, selected output stage, reference clock,
frequency step, and so on); refer to

Chapter 8: Application information

for more details.

14/53

STW81102 Typical performance characteristics

s

3 Typical performance characteristics

Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop
measurements are done with F

STEP

properly set. The loop filter configuration is depicted in

diagram

, and the reference clock signal is at 76.8 MHz with phase noise of -135 dBc/Hz at

1kHz offset, -145 dBc/Hz at10 kHz offset and -149.5 dBc/Hz of noise floor.

Figure 3. VCO A (direct output) open loop

phase noise

=200 kHz, with the F

Figure 4. VCO B (direct output) open loop

phase noise

and charge pump current

PFD

Figure 36: Typical application

Figure 5. VCO A (direct output) closed loop

phase noise at 3.6GHz
(F
I

1.2° rms

STEP

=3mA)

CP

=200kHz; F

=200kHz;

PFD

Figure 6. VCO B (direct output) closed loop

phase noise at 4.3GHz
(F
I

1.4° rm

STEP

=4mA)

CP

=200kHz; F

=200kHz;

PFD

15/53

Typical performance characteristics STW81102

0.5

0.5

s

0

0

s

Figure 7. VCO A (div. by 2 output) closed

loop phase noise at 1.65GHz
(F
I

STEP

=2mA)

CP

° rms

=200kHz; F

=400kHz;

PFD

Figure 9. VCO A (div. by 4 output) closed

loop phase noise at 825MHz
(F
I

STEP

=1.5mA)

CP

=200kHz; F

=800kHz;

PFD

Figure 8. VCO B (div. by 2 output) closed

loop phase noise at 2.15GHz
(F
I

STEP

=3mA)

CP

7° rm

=200kHz; F

=400kHz;

PFD

Figure 10. VCO B (div. by 4 output) closed

loop phase noise at 1.075GHz
(F
I

STEP

=2.5mA)

CP

=200kHz; F

=800kHz;

PFD

.2° rms

16/53

.24° rm

STW81102 Typical performance characteristics

Figure 11. PFD frequency spurs (direct

output; F

-73 dBc

@200KHz

=200kHz)

PFD

Figure 13. PFD frequency spurs (div. by 4

output; F

=800kHz)

PFD

Figure 12. PFD frequency spurs (div. by 2

output; F

-83 dBc

@400KHz

=400kHz)

PFD

Figure 14. Settling time (final frequency=2.15

GHz; F

=400kHz; ICP=3mA)

PFD

-91 dBc

@800KHz

17/53

General description STW81102

4 General description

Figure 1: Block diagram

PLL frequency synthesizer.

The STW81102 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a
divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit
programmable reference divider, two programmable counters and a programmable dual­modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual­modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P
+A. The division ratio of both reference and VCO dividers is controlled through the selected
digital interface (I

The digital interface type is selected by the proper hardware connection of the pin
DBUS_SEL (0 V for I

All devices operate with a power supply of 3.3 V and can be powered down when not in use.

shows the separate blocks that, when integrated, form an Integer-N

2

C bus or SPI).

2

C bus, 3.3 V for SPI).

18/53

STW81102 Circuit description

5 Circuit description

5.1 Reference input stage

The reference input stage is shown in
F

input while the inverter used as the frequency reference buffer is AC coupled.

ref

Figure 15. Reference frequency input buffer

VDD

F

ref

Figure 15

. The resistor network feeds a DC bias at the

INV

Power Down

BUF

5.2 Reference divider

The 10-bit programmable reference counter allows division of the input reference frequency
to produce the input clock to the PFD. The division ratio is programmed through the digital
interface.

5.3 Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it
down to a manageable frequency for the CMOS A and B counters. The modulus P is
programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5
core whose division ratio depends on the state of the modulus input.

19/53

Circuit description STW81102

5.4 A and B counters

The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus
(16/17 or 19/20) prescaler, make it possible to generate output frequencies which are
spaced only by the reference frequency divided by the reference division ratio. Thus, the
division ratio and the VCO output frequency are given by these formulas:

NBPA+×=

F

VCO

BPA+×()F

----------- ------------- ------------- ---------- ----=

×

ref

R

where:

F

: output frequency of VCO

VCO

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface)

B: division ratio of the main counter

A: division ratio of the swallow counter

F

: input reference frequency

ref

R: division ratio of reference counter

N: division ratio of PLL

For a correct working of the VCO divider, B must be strictly higher than A. A can take any
value ranging from 0 to 31. The range of N can vary from 256 to 65551 (P=16) or from 361
to 77836 (P=19).

Figure 16. VCO divider diagram

VCOBUF-

Prescaler

16/17 or 19/20

VCOBUF+

modulus

5-bit 12-bit

A-counter

20/53

To PFD

B-counter

STW81102 Circuit description

5.5 Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output
proportional to the phase error. The PFD includes a delay gate that controls the width of the
anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer
function.

Figure 17

is a simplified schematic of the PFD.

Figure 17. PFD diagram

5.6 Lock detect

VDD

F

ref

F

ref

VDD

DFF

R

R

DFF

Up

Delay

Down

ABL

This signal indicates that the difference between rising edges of both UP and DOWN PFD
signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is
high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes
current only during PLL transients.

5.7 Charge pump

This block drives two matched current sources, IUP and I
respectively by UP and DOWN PFD outputs. The nominal value of the output current is
controlled by an external resistor (connected to the REXT input pin) and a 3-bit word that
allows selection among 8 different values.

The minimum value of the output current is: I

, which are controlled

DOWN

= 2*VBG/REXT (VBG~1.17 V)

MIN

21/53

Circuit description STW81102

Table 7. Current value vs. selection

CPSEL2 CPSEL1 CPSEL0 Current Value for REXT=4.7 KΩ

000I

0012*I

0103*I

0114*I

1005*I

1016*I

1107*I

1118*I

MIN

MIN

MIN

MIN

MIN

MIN

MIN

MIN

0.5 mA

1.0 mA

1.5 mA

2.0 mA

2.5 mA

3.0 mA

3.5 mA

4.0 mA

Note: The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are

forced to VDD/2

Figure 18. Loop filter connection

VDD

BUF

VCTRL

C3

R3

BUF

Charge

Pump

ICP

R1

C2

C1

Cal bit

22/53

STW81102 Circuit description

5.8 Voltage controlled oscillators

5.8.1 VCO selection

The STW81102 integrates two low-noise VCOs to cover a wide band from:

● 3000 MHz to 3620 MHz and 4000 MHz to 4650 MHz (direct output)

● 1500 MHz to 1810 MHz and 2000 MHz to 2325 MHz (selecting divider by 2)

● 750 MHz to 905 MHz and 1000 MHz to 1162.5 MHz (selecting divider by 4)

The frequency range is 3000 MHz to 3620 MHz for VCO A and 4000 MHz to 4650 MHz for
VCO B.

5.8.2 VCO frequency calibration

Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting
capacitors from the resonator. These frequency ranges are intended to cover the wide band
of operation and compensate for process variation on the VCO center frequency.

The range is automatically selected when the

SERCAL bit is set to 1. The charge pump is
inhibited, and the ICP and VCTRL pins are at VDD/2 volts. The ranges are then tested with
this VCO input voltage to select the one nearest to the desired output frequency (F
N*F

/R).

ref

OUT

=

After this selection, the SERCAL bit is automatically reset to 0 and the charge pump is once
again enabled. To enable a fast settle, t
VDD/2 on the loop filter to reach F

he PLL needs only to perform fine adjustment around

.

OUT

Figure 19. VCO sub-bands frequency characteristics

23/53

Circuit description STW81102

The SERCAL bit should be set to 1 at each division ratio change. VCO calibration procedure
takes approximately 7 periods of the PFD frequency.

The maximum allowed F
higher F

, follow the steps below:

PFD

to perform the calibration process is 1 MHz. When using a

PFD

1. Calibrate the VCO at the desired frequency with an F

2. Set the A, B and R divider ratios for the desired F

VCO calibration auto-restart feature

The VCO calibration auto-restart feature, once activated, allows to restart the calibration
procedure when the Lock Detector reports that the PLL has moved to an unlock condition
(trigger on ‘1’ to ‘0’ transition of Lock Detector signal).

This situation could happen if the device experiences a significant temperature variation.
Once programmed at the initial temperature T
(-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature
drift (in either direction) is within the limit specified by the ΔT
final temperature T

is still inside the nominal range.

1

Each VCO featured by STW81102 has its specific ΔT
is typically lower than the maximum allowable drift (ΔT
vice versa).

By enabling the VCO Calibration Auto-Restart feature (through the CAL_AUTOSTART_EN
bit), the part will be able to select again the proper VCO frequency sub-range if the
temperature drift exceeds the ΔT

limit, without any external user command.

LK

5.8.3 VCO voltage amplitude control

less than 1 MHz.

PFD

.

PFD

inside the operating temperature range

0

parameter, provided that the

LK

parameter reported in Table 5, that

LK

=125; from -40 °C to +85 °C and

MAX

The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated
programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise,
whereas lower amplitudes save power.

Ta bl e 8

gives the voltage swing level expected on the resonator nodes, the current

consumption, and the phase noise at 1 MHz.

Table 8. VCO A performances versus amplitude setting (freq=3.3GHz)

PLL_A[1:0]

00 1.1 16 -125

01 1.3 18 -126

10 1.9 27 -128.5

11 2.1 30 -129

Differential voltage swing

(Vp)

Current consumption

(mA)

PN @1MHz (dBc/Hz)

24/53

STW81102 Circuit description

Table 9. VCO B performances versus amplitude setting (freq=4.3GHz)

PLL_A[1:0]

00 1.1 11 -124

01 1.3 14 -125

10 1.9 20 -127.5

11 2.1 22 -128

Differential voltage swing

(Vp)

5.9 Output stage

The differential output signal of the synthesizer can be selected by software among three
different signal paths (Direct, Divider by 2 and Divider by 4) providing multi-band capability.

The selection of the output stage is done by programming properly the PD[4:0] bits.

The output stage is an open-collector structure which is able to meet different requirements
over the desired output frequency range by proper connections on the PCB. Refer to

Chapter 8: Application information

5.9.1 Output Buffer control mode

This control mode allows to enable/disable the output stage by a hardware control pin
(EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very
fast switching time is achieved.

Current consumption

(mA)

for more details on PCB connections.

PN @1MHz (dBc/Hz)

This feature can be useful in designing a ping-pong architecture saving the cost of an
external RF switch.

The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in

Ta bl e 1 0.

Table 10. EXT_PD pin function setting

OUTBUF_CTRL_EN Function of the EXT_PD pin EXT_PD pin settings

0 Device hardware power down

1 Output Buffer control

EXT_PD = 0V Î Device ON

EXT_PD = 3.3V Î Device OFF

EXT_PD = 0V Î Output Stage ON

EXT_PD = 3.3V Î Output Stage OFF

25/53

Circuit description STW81102

5.10 External VCO Buffer

Although the main benefits of the STW81102 are the two wideband and low-noise VCOs,
the capability to use an external VCO is also provided.

The external VCO Buffer is able to manage a signal coming from an external VCO in order
to build a synthesizer using the STW81102 only as PLL IC. The output signal of the
synthesizer can also be taken from the output section of the STW81102 (direct, divided by 2
or divided by 4 by) by properly setting the PD[4:0] bits, thus providing additional flexibility.

The external VCO signal can range from 625 MHz up to 5 GHz and its minimum power level
must be -10 dBm.

26/53

STW81102 I2C bus interface

6 I2C bus interface

The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V.

Data is transmitted from microprocessor to the STW81102 through the 2-wire (SDA and

2

SCL) I

The I
any device that reads the data as a receiver. The device controlling the data transfer is the
master, and the others are slaves. The master always initiates the transfer and provides the
serial clock for synchronization.

6.1 General features

6.1.1 Data validity

Data changes on the SDA line must only occur when the SCL is low. SDA transitions while
the clock is high are used to identify a START or STOP condition.

Figure 20. Data validity

C bus interface. The STW81102 is always a slave device.

2

C bus protocol defines any device that sends data on the bus as a transmitter, and

SDA

SCL

Data line Change
Stable data data
Valid allowed

6.1.2 START and STOP conditions

START condition

A START condition is identified by a transition of the data bus SDA from high to low while the
clock signal SCL is stable in the high state. A START condition must precede any data
transfer command.

STOP condition

A STOP condition is identified by a transition of the data bus SDA from low to high while the
clock signal SCL is stable in the high state. A STOP condition terminates communications
between the STW81102 and the bus master.

27/53

I2C bus interface STW81102

A
L

/

/

Figure 21. START and STOP conditions

SCL

SDA

START

6.1.3 Byte format and acknowledge

Every byte put on the SDA line must be 8 bits long, and be followed by an acknowledge bit
to indicate a successful data transfer. Data is transferred with the most significant bit (MSB)
first. The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock
pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data.

Figure 22. Byte format and acknowledge

SC

SD

START

MSB

6.1.4 Device addressing

2 3 7

/

/

STOP

8 91

Acknowledgement

from receiver

The master must first initiate with a START condition to communicate with the STW81102,
and then send 8 bits (MSB first) on the SDA line which correspond to the device select
address and the read or write mode.

The first 7 MSBs are the device address identifier, which corresponds to the I2C bus
definition. For the STW81102, the address is set at “1100A2A1A0”, 3 bits programmable.
The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and
to 0 in write mode.

Following a START condition, the STW81103 identifies the device address on the bus and, if
matched, acknowledges the identification on the SDA bus during the 9th clock pulse.

28/53

STW81102 I2C bus interface

6.1.5 Single-byte write mode

Following a START condition, the master sends a device select code with the RW bit set to

0. The STW81102 sends an acknowledge and waits for the 1-byte internal sub-address that
provides access to the internal registers.

After receiving the sub-address internal byte, the STW81102 again responds with an
acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE
register, a single-byte write with sub-address 04H changes the CONTROL register, and so
on.

Table 11. Single-byte write mode

S 1100A

0 ack sub-address byte ack DATA IN ack P

2A1A0

6.1.6 Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data
bytes, and each one is acknowledged. The master then terminates the transfer by
generating a STOP condition.

The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H
and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H),
and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81102
registers.

Table 12. Multi-byte write mode

S 1100A2A1A00 ack sub-address byte ack DATA IN ack .... DATA IN ack P

6.1.7 Current byte address read mode

In the current byte address read mode, following a START condition, the master sends the
device address with the RW bit set to 1. Note that no sub-address is needed since there is
only one read register. The STW81102 acknowledges this and outputs the data byte. The
master does not acknowledge the received byte, and terminates the transfer with a STOP
condition.

Table 13. Current byte address read mode

S 1100 A2 A1 A

0

1ack DATA OUT No ackP

29/53

I2C bus interface STW81102

6.2 Timing specification

Figure 23. Data and clock

SDA

SCL

t

cwl

t

cs

Table 14. Data and clock timing specifications

t

ch

Symbol Parameter Minimum time Units

t

t

t

cs

t

ch

cwh

cwl

Data to clock setup time 2 ns

Data to clock hold time 2 ns

Clock pulse width high 10 ns

Clock pulse width low 5 ns

Figure 24. Start and stop

SDA

SCL

t

cwh

tt

start stop

30/53

STW81102 I2C bus interface

Table 15. Start and stop timing specifications

Symbol Parameter Minimum time Units

t

start

t

stop

Figure 25. Ack

Clock to data start time 2 ns

Data to clock down stop time 2 ns

SDA

89

SCL

t

d1

Table 16. Ack timing specifications

t

d2

Symbol Parameter Minimum time Units

t

d1

t

d2

Ack begin delay 2 ns

Ack end delay 2 ns

31/53

I2C bus interface STW81102

6.3 I2C registers

The STW81102 has 6 write-only registers and 1 read-only register.

6.3.1 Write-only registers

Ta bl e 1 7

Table 17. Write-only registers

gives a short description of the write-only registers.

HEX code DEC code Description

0x00 0 FUNCTIONAL_MODE

0x01 1 B_COUNTER

0x02 2 A_COUNTER

0x03 3 REF_DIVIDER

0x04 4 CONTROL

0x05 5 CALIBRATION

FUNCTIONAL_MODE

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

OUTBUF_
CTRL_EN

CAL_AUT
OSTART_

EN

PD4 PD3 PD2 PD1 PD0 B11

OUTBUF_CTRL_EN: Output Buffer control mode enable (0 = Off; 1 = ON)

CAL_AUTOSTART_EN: VCO calibration auto-restart enable (0 = Off; 1 = ON)

The bits PD[4:0] allow to select different functional modes for the STW81102 synthesizer
according to the

Table 18. Functional modes

Decimal value Description

32/53

Table 18

0 Power down mode

1 Enable VCO A, output frequency divided by 2

2 Enable VCO B, output frequency divided by 2

3 Enable external VCO, output frequency divided by 2

4 Enable VCO A, output frequency divided by 4

5 Enable VCO B, output frequency divided by 4

6 Enable external VCO, output frequency divided by 4

7 Enable VCO A, direct output

.

STW81102 I2C bus interface

Table 18. Functional modes (continued)

Decimal value Description

8 Enable VCO B, direct output

9 Enable external VCO, direct output

B_COUNTER

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

B10B9B8B7B6B5B4B3

B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register)

A_COUNTER

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

B2 B1 B0 A4 A3 A2 A1 A0

Bits B[2:0] for B_COUNTER, A_COUNTER values.

REF_DIVIDER

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

R9 R8 R7 R6 R5 R4 R3 R2

Reference clock divider ratio R[9:1] (bits R1, R0 in the next register).

CONTROL

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

R1 R0 PLL_A1 PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL

The CONTROL register is used to set the charge pump current, the VCO output voltage
amplitude and the prescaler modulus:

PLL_A[1:0]: VCO amplitude

CPSEL[2:0]: charge pump output current

PSC_SEL: prescaler modulus select ('0' for P=16, '1' for P=19)

33/53

I2C bus interface STW81102

The LO output frequency is programmed by setting the proper values for A, B and R
according to the following formula:

F

REF CLK–

F

OUTDR

BPA+×()×

------------ ----------------- --

×=

R

1 for direct output

where D

equals

R

and P is the selected prescaler modulus.

CALIBRATION

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0

This register controls the VCO calibrator using the following values:

INITCAL: for test purposes only; must be set to 0.

SERCAL: at 1, starts the VCO auto-calibration (automatically reset to 0 at the end of calibration)

SELEXTCAL: for test purposes only; must be set to 0

CAL[4:0]: for test purposes only; must be set to 0

6.3.2 Read-only register

MSB LSB

0.5 for output divided by 2

{

0.25 for output divided by 4

b7 b6 b5 b4 b3 b2 b1 b0

DEV_ID1 DEV_ID0 LOCK_DET INTCAL4 INTCAL3 INTCAL2 INTCAL1 INTCAL0

This register is automatically addressed in the 'current byte address read mode', using the
following values:

DEV_ID[1:0]: device identifier bits; returns 01

LOCK_DET: 1 when PLL is locked

INTCAL[4:0]: internal value of the VCO control word

6.3.3 Default configuration

At power on, all the bits are set to ‘0’. Consequently the part starts in power down mode.

34/53

STW81102 I2C bus interface

6.4 VCO calibration procedure

Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION
register bit[6]) is set to 1.

To program the device properly while ensuring VCO calibration, perform the following steps
before every channel change:

1. Program all the registers using a multi-byte write sequence with the desired settings

(functional mode, B and A counters, R counter, VCO amplitude, charge pump,
prescaler modulus), and all the bits of the CALIBRATION register (05H) set to 0.

2. Program the CALIBRATION register using a single-byte write sequence (subaddress

05H) with the SERCAL bit set to 1.

The maximum allowed PFD frequency (F

PFD

higher than 1 MHz, perform the following additional steps:

● Perform all the steps of the calibration procedure, making sure to program the desired

VCO frequency with proper settings for the R, B and A counters so that F

● Program the device with the desired VCO and PFD frequency settings according to

step 1) above.

6.4.1 VCO calibration auto-restart feature

The VCO calibration auto-restart feature can be enabled in two steps:

1. set the desired frequency ensuring VCO calibration as described above (section 6.4)

2. program the FUNCTIONAL_MODE register (sub-address 00H) using a single-byte

write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged
the others.

) during calibration is 1 MHz; if you want a F

is ≤ 1 MHz.

PFD

PFD

35/53

SPI digital interface STW81102

7 SPI digital interface

7.1 General features

The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to

3.3 V.

The STW81102 IC is programmed by means of a high-speed serial-to-parallel interface with
write option only. The 3-wire bus can be clocked at a frequency as high as 100 MHz to allow
fast programming of the registers containing the data for RF IC configuration.

The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs
represent the address of the registers, and the 24 LSBs represent the value of the registers.

Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.

The outputs of the selected register are sent to the device on the rising edge of the LOAD
signal.

Figure 26. SPI input and output bit order

Last bit sent
(LSB)0

DATA

2

1

232425(MSB)

LOAD

Reg.#0

Reg.#1

Address

decoder

D23 (MSB)

D0 (LSB)

A1

LOAD #4

Reg.#4

36/53

STW81102 SPI digital interface

Table 19. SPI data structure (MSB is sent first)

MSB LSB

Address Data for register (24 bits)

A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 20. Address decoder and outputs

Address Outputs

A1 A0

Data bits

D23-D0

00 24 0ST1

0 1 24 1 ST2 Functional modes, VCO dividers

10 24 2ST3Reserved

11 24 3ST4Reserved

7.2 Timing specification

Figure 27. SPI timing specification

tsetup

thold

Data

Clock

Load

MSBMSB-1 LSB

tdk

No Name Function

Reference divider, VCO amplitude, VCO calibration,
charge pump current, prescaler modulus

t

clk_loadr tload

t

clk_loadf

Table 21. SPI timing specification

Parameter Description Min. Typ. Max. Units

t

setup

t

hold

t

clk

t

load

t

clk_loadr

t

clk_loadf

Data to clock setup time 0.8 ns

Data to clock hold time 0.2 ns

Clock cycle period 10 ns

Load pulse width 3 ns

Clock to load rising edge 2 ns

Clock to load falling edge 0.5 ns

37/53

SPI digital interface STW81102

7.3 Bit tables

Table 22. Bits at 00h and ST1

Serial interface address = 00h Register name = ST1

Bit Name Description

[23] R9

[22] R8

[21] R7

[20] R6

[19] R5

Reference clock divider ratio

[18] R4

[17] R3

[16] R2

[15] R1

[14] R0

[13] PLL_A1

VCO amplitude control

[12] PLL_A0

[11] CPSEL2

Charge pump output current control[10] CPSEL1

[9] CPSEL0

[8] PSC_SEL Prescaler modulus select (0 for P=16, 1 for P=19)

[7] INITCAL For test purposes only; must be set to 0

[6] SERCAL Enable VCO calibration (see

Section 7.4

)

[5] SELEXTCAL For test purposes only; must be set to 0

[4] CAL4

[3] CAL3

[2] CAL2

For test purposes only; must be set to 0

[1] CAL1

[0] CAL0

38/53

STW81102 SPI digital interface

Table 23. Bits at 01h and ST2

Serial interface address = 01h Register name = ST2

Bit Name Description

[23] OUTBUF_CTRL_EN Output buffer control mode enable (0 = Off, 1 = On)

[22] CAL_AUTOSTART_EN VCO calibration auto restart enable (0 = Off, 1 = On)

[21] PD4

[20] PD3

[19] PD2

[18] PD1

[17] PD0

[16] B11

[15] B10

[14] B9

[13] B8

[12] B7

[11] B6

[10] B5

[9] B4

[8] B3

Device functional modes:

0. Power down

1. Enable VCO A, output frequency divided by 2

2. Enable VCO B, output frequency divided by 2

3. Enable external VCO, output frequency divided by 2

4. Enable VCO A, output frequency divided by 4

5. Enable VCO B, output frequency divided by 4

6. Enable external VCO, output frequency divided by 4

7. Enable VCO A, direct output

8. Enable VCO B, direct output

9. Enable external VCO, direct output

B_COUNTER bits

[7] B2

[6] B1

[5] B0

[4] A4

[3] A3

[2] A2

[1] A1

[0] A0

A_COUNTER bits

39/53

SPI digital interface STW81102

The LO output frequency is programmed by setting the proper values for A, B and R
according to the following formula:

F

REF CLK–

F

OUT

D

BPA+×()×

R

------------ ----------------- ------

×=

R

1 for direct output

where D

and P is the selected prescaler modulus.

equals

R

0.5 for output divided by 2

{

0.25 for output divided by 4

7.3.1 Default configuration

At power on, all the bits are set to ‘0’. Consequently the part starts in power down mode.

7.4 VCO calibration procedure

Calibration of the VCO center frequency is activated when the SERCAL bit (ST1 register
bit[6]) is set to 1.

To program the device properly while ensuring VCO calibration, perform the following steps
before every channel change:

1. Program the ST2 register with the desired settings (functional mode, B and A

counters).

2. Program the ST1 register with the desired settings (R counter, VCO amplitude, charge

pump, prescaler modulus) and with the SERCAL bit set to 1.

The maximum allowed PFD frequency (F
higher than 1 MHz, perform the following additional steps:

● Perform all the steps (step 1 and 2 above) of the calibration procedure, making sure to

program the desired VCO frequency with proper settings of the R, B and A counters so
that F

● Program the device with the desired VCO and PFD frequency settings as per steps 1

and 2 above with SERCAL bit set to 0.

is ≤ 1 MHz.

PFD

) during calibration is 1 MHz; if you want a F

PFD

PFD

7.4.1 VCO calibration auto-restart feature

The VCO calibration auto-restart feature can be enabled in two steps:

1. set the desired frequency ensuring VCO calibration as described above (

2. program the ST2 register with the CAL_AUTOSTART_EN bit set to '1' while keeping

unchanged the others.

40/53

Section 7.4

)

STW81102 Application information

8 Application information

The STW81102 features three different alternately selectable bands: direct output (3.0 to

3.62 GHz and 4.0 to 4.65 GHz), divided by 2 (1.5 to 1.81 GHz and 2.0 to 2.325 GHz) and
divided by 4 (750 to 905 MHz and 1000 to 1162.5 MHz). To achieve a suitable power level, a
good matching network is necessary to adapt the output stage to a 50 Ω load. Moreover,
since most commercial RF components have single-ended input and output terminations, a
differential to single-ended conversion may be required.

The different matching configurations shown below for each of the three bands are
suggested as a guideline when designing your own application board.

Inside the evaluation kit is the ADS design for each matching configuration suggested in this
chapter. The name of the corresponding ADS design is given in each figure.

The ADS designs provide only a first indication of the output stage matching, and should be
reworked according to the choices of layout, board substrate, components and so on.

The ADS designs of the evaluation boards are provided with a complete electromagnetic
modelling (board, components, and so on).

8.1 Direct output

If you do not need a differential to single conversion, you can match the output buffer of the
STW81102 in the simple way shown in
ended output network in the 3.0 - 4.65GHz range (MATCH_LC_LUMP_4G_DIFF.dsn).

Figure 28. Differential/single-ended output network

(MATCH_LC_LUMP_4G_DIFF.dsn)

RF

RF

OUTP

OUTN

100 ohm

100 ohm

Figure 28

Vcc

. This illustrates the differential to single-

5.5nH

10pF

10pF

5.5nH

50 ohm

50 ohm

Vcc

Since most discrete components for microwave applications are single-ended, you can
easily use one of the two outputs and terminate the other one to 50 Ω with a 3 dB power
loss.

41/53

Application information STW81102

Alternatively, you can combine the two outputs in other ways. A first topology for the direct
output (3 GHz to 4.65 GHz) is suggested in

Figure 29

. It basically consists of a simple LC
balun and a matching network to adapt the output to a 50 Ω load. The two LC networks shift
output signal phase of -90° and +90°, thus combining the two outputs. This topology,
designed for a center frequency of 4 GHz, is intrinsically narrow-band since the LC balun is
tuned at a single frequency. If the application requires a different sub-band, the LC combiner
can be easily tuned to the frequency of interest.

Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn)

Vcc

0.8pF

0.8pF

1.9nH

0.8pF 2.5pF

1.9nH

0.8pF

50 ohm

RF

RF

50 ohm

OUTP

OUTN

50 ohm

1.9nH

1.9nH

Vcc

The 1.9 nH shunt inductor works as a DC feed for one of the open collector terminals as well
as a matching element along with the other components. The 1.9 nH series inductors are
used to resonate the parasitic capacitance of the chip.

For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and
0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths
to minimize losses and undesired impedance shift.

An alternative topology that permits a more broadband matching as well as balanced to
unbalanced conversion, is shown in

42/53

Figure 30

.

STW81102 Application information

Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn)

Vcc

RF

RF

50 ohm

OUTP

OUTN

50 ohm

5.5nH

12pF

12pF

5.5nH

Vcc

For differential to single conversion, the 50 to 100 Ω Johanson balun is recommended
(3700BL15B100).

8.2 Divided by 2 output

If your application does not require a balanced to unbalanced conversion, the output
matching reduces to the simple circuit shown below (
differential to single-ended output network in the 1.5 - 2.325 GHz range
(MATCH_LC_LUMP_2G_DIFF.dsn). You can easily use this solution to provide one single­ended output that terminates the other output at 50 Ω with a 3 dB power loss.

2:1

4.7pF12pF

1pF 1pF 1.2pF 1.2pF

Figure 31

), which illustrates a

50 ohm

Figure 31. Differential/single-ended output network

(MATCH_LC_LUMP_2G_DIFF.dsn)

Vcc

RF

RF

50 ohm

OUTP

OUTN

50 ohm

22nH

10pF

10pF

22nH

Vcc

43/53

50 ohm

50 ohm

Application information STW81102

A first solution to combine the differential outputs is the lumped LC type balun tuned in the
2 GHz band (

Figure 32

).

Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn)

Vcc

2pF

2pF

2.7nH

2pF 3pF

2.7nH

2pF

50 ohm

3nH

RF

RF

50 ohm

OUTP

OUTN

50 ohm

2.7nH

2.7nH

Vcc

The same recommendation for the SMD components also applies to the divided by 2 output.

Another topology suited to combining the two outputs for the divided by 2 frequencies is
represented in

Figure 33

.

Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn)

Vcc

50 ohm

RF

OUTP

RF

OUTN

50 ohm

44/53

5.5nH

22pF

22pF

5.5nH

Vcc

2:1

22pF

1.9nH

1.2pF

50 ohm

STW81102 Application information

For differential to single conversion, the 50 to 100 Ω Johanson balun (1600BL15B100) is
recommended.

8.3 Divided by 4 output

The topology, components, values and considerations of

Figure 31

also apply to the divided

by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn).

As for the previous sections, a solution to combine the differential outputs is the lumped LC
type balun tuned in the 1 GHz band (

Figure 34

).

Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn)

Vcc

RF

RF

25 ohm

OUTP

OUTN

25 ohm

5.5nH

5.5nH

4pF

4pF

5.5nH

4pF 6pF

5.5nH

4pF

14nH

50 ohm

Vcc

If you prefer to use an RF balun, you can adapt the topology depicted in
change the balun and the matching components (

Figure 35

). The suggested balun for the

0.75 - 1.17 GHz frequency range is the 1:1 Johanson 900BL15C050.

45/53

Figure 33

, and

Application information STW81102

Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn)

Vcc

25 ohm

RF

OUTP

RF

OUTN

25 ohm

8.4 Evaluation kit

An evaluation kit can be delivered upon request, including the following:

● Evaluation board

● GUI (graphical user interface) to program the device

● Measured S parameters of the RF output

● ADS2005 schematics providing guidelines for application board design

● STWPLLSim software for PLL loop filter design and noise simulation

● Application program interface (API)

Vcc

18nH

8.2pF

8.2pF

18nH

1:1

22pF

2.1nH

0.5pF

50 ohm

Three different evaluation kits are available, each optimized for one of the following
frequency ranges:

● 1 GHz

● 2 GHz

● 4 GHz

When ordering, please specify one of the following order codes:

Table 24. Order code of the evaluation kit

Part number Description

STW81102-EVB1G 1GHz frequency range - divider by 4 output optimized

STW81102-EVB2G 2GHz frequency range - divider by 2 output optimized

STW81102-EVB4G 4GHz frequency range - direct output optimized

The three evaluation kits differ only for the output stage network and can be adapted from
one frequency band variant to a different one replacing properly the matching components
and the balun.

46/53

STW81102 Application diagrams

9 Application diagrams

Figure 36. Typical application diagram

From/to microcontroller

RF Out

VDD

VDD

1

10P22p1n

1

10P22p1n

VDD

VDD

VDD_VCOA DBUS_SEL

VDD_DIV 2

1

1

VDD_O UTBUF

OUTBUFP

OUTBUFN

VDD_DIV 4

VDD_VCOB

2.2K

270p 68p

ADD1

ADD2

STW81102

STW 81103

VCTRL

VDD_ESD

8.2K

2.7n

100

15p

100100

15p 15p

I2C

SDA/DATA

VDD_CP

EXT_PD

VDD_BUFV CO

EXTVCO_INP

EXTVCO_INN

TE ST1

VDD

VDD_PLL

REF_CLK

TEST2

LOCK_DET

1

10µ22p1n

SPI

1.8n

VDD

2

10P22p1n

ref clk

51

SCL/CLK

ADD0/LOAD

ICP

REXT

4.7K

VDD_DBUS

to microcontrollerloop filter

Note: 1 See Chapter 8: Application information for further information on output matching topology.

2

2 EXT_PD, ADD2, ADD1 (and ADD0 when the I

C bus is selected) can be hard wired directly

on the board.

3 Loop filter values are for F

4 For best performance VDD

= 200 kHz.

STEP

must be a low noise supply (20 μV

1

47/53

in 10 Hz-100 kHz BW).

RMS

Application diagrams STW81102

Figure 37. Ping-pong architecture diagram

5)2XW

9''

9''

ORRSILOWHU

Q

 S S

QSM

9''

B

9''



9''



Q S  M Q  S M

9''





B

QSM

N



9 ''B(6 '

9 &75/

, &3

9''B9&2%

9''B',9

287%8)1

67:

287%8)3

'HYLFH /RFNHG DW) UHT )

2XWSXW%XIIHU&RQWURO0RGHHQDEOHG

9''B287%8)

9''B',9

9''B9&2$

$''/2$'

$''

$ ''

N

5 (;7

9''B&3

 6'$' $7$

6&/&/.

PLFURFRQWUROOHU

9''

9''

9''

9''

B

Q S  M

QSM

B





Q S  M

$ ''

$''

9 ''B9& 2$

9 ''B' ,9

9 ''B2 87%8 )

2 87%8 )3

2 87%8 )1

9 ''B' ,9

9 ''B9& 2%

$''/2$'

67:

'HYLFH /RFNHG DW) UHT )

2XWSXW%XIIHU&RQWURO0RGHHQDEOHG

9&75/

, &3

9 ''B(6'

6&/&/.

 6'$' $7$

5 (;7

9 ''B& 3



QSM

7 (6 7

( ;79&2 B,1 1



( ;79&2 B ,13

9' 'B%8 )9&2

(; 7B3'

(;7B3'

9' 'B%8 )9&2

( ;79&2 B ,13

 (;7 9&2 B,1 1



7 (67

9''

/2& .B'(7

7(67 

5 ()B &/.

9'' B3//

'%86B6(/

9''B'%86

2XWSXW%XI IHU 

9''B'%86

'%86B6(/

9' 'B3//

5 ()B& /.

/ 2& .B'(7

WRPLFURFRQWUROOHU

B

63,

,&

+:&RQWURO

9''

,&

63,

Q S  M

7 (67

Q

9''

Q

UHIFON

B

B



 S S

N

Q

N

9''

QSM

B

WRPLFURFRQWUROOHUORRSILOWHU 

Note: 1 See Chapter 8: Application information for further information on output matching topology.

2

2 EXT_PD, ADD2, ADD1 (and ADD0 when the I

C bus is selected) can be hard wired directly

on the board.

3 Loop filter values are for F

4 For best performance VDD

STEP

1_1

= 200 kHz.

and VDD

must be low noise supplies (20 μV

1_2

RMS

in 10 Hz-

100 kHz BW).

48/53

STW81102 Application diagrams



Figure 38. Application diagram with external VCO (LO output from STW81102)

)URPWR PLFURFRQWUROOHU

/22XW

9''



9''

QSM

$''

$''

9''B9& 2$ '%86B6(/





9''

9''





Q S  M

9''B' ,9

9''B28 7%8)

287%8) 3

287%8) 1

9''B ',9

9''B9& 2%

9''B(6'

67:

9&75 /

6&/ &/.

$''/ 2$'

,&3

5(;7

6'$'$7$

9''B&3

9''B'%86

(;7B3'

9''B%8 )9&2

(;79&2 B,13

(;79&2 B,11

9''B3//

5()B&/.

7(67 

7(67

/2&. B'(7

9''



,&

63,

287

9&75/

9''



UHIFON

Q

&

Q S  M

N

9''

QSM



&

5

5

&

WR PLF URFRQWUROOHU

ORRSILOWHU

Note: See Chapter 8: Application information for further information on output matching topology.

Figure 39. Application diagram with external VCO (LO output from VCO)

)URPWR PLFURFRQWUROOHU

Q S  M

$''

$''

9''B9& 2$ '%86B 6(/

9''B' ,9

9''B 28 7%8)

287%8) 3

287%8) 1

67:

6&/ &/.

$''/ 2$'

6'$'$7$

9''B'%86

(;7B3'

9''B %8) 9&2

(;79&2 B ,13

(;79&2 B ,11

9''B 3//

9''B' ,9

9''B9& 2%

9&75 /

,&3

9''B(6'

5(;7

5()B&/.

7(67

7(67

9''B&3

/2&. B' (7

,&

63,

9''

Q



9''





UHIFON

/22XW







287

9&75/

&

N

9''

QSM



&

5

5

&

WR PLFURFRQWUROOHU

ORRSILOWHU

49/53

Package mechanical data STW81102

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages, which have a lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: http://www.st.com.

Figure 40. VFQFPN28 mechanical drawing (

Note 1

)

Note: 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.

(Very thin: A=1.00 Max)

2 Details of the terminal 1 identifier are optional, but if given, must be located on the top

surface of the package by using either a mold or marked features.

50/53

STW81102 Package mechanical data

Table 25. Package dimensions

Ref. Min. Typ. Max. Unit

A 0.800 0.900 1.000 mm

A1 0.020 0.050 mm

A2 0.650 1.000 mm

A3 0.200 mm

b 0.180 0.250 0.300 mm

D 4.850 5.000 5.150 mm

D1 4.750 mm

D2 2.950 3.100 3.250 mm

E 4.850 5.000 5.150 mm

E1 4.750 mm

E2 2.950 3.100 3.250 mm

e 0.500 mm

L 0.350 0.550 0.750 mm

P 0.600 mm

K 14 degrees

ddd 0.080 mm

51/53

Ordering information STW81102

11 Ordering information

Table 26. Order codes

Part number Temp range, ° C Package Packing

STW81102AT -40 to 85 VFQFPN28 Tray

STW81102ATR -40 to 85 VFQFPN28 Tape and reel

12 Revision history

Table 27. Document revision history

Date Revision Changes

06-Mar-2006 1 Initial release.

Changed from preliminary data to maturity.

16-Jun-2006 2

20-Jul-2007 3

Updated

information

Added information usage of prescaler with modulus 16/17 for VCO
higher than 3300MHz in

Section 5.3: Prescaler

Moved the ordering information to

Section 2: Electrical specifications; Section 8: Application

and

Section 9: Application diagrams

Section 2.4: Electrical specifications

and

Section 5.4: A and B counters

Chapter 11

.

,

.

.

14-Aug-2007 4

23-Jan-2008 5

Updated
in

Updated
Updated

application diagram)
Phase noise specification

Updated
Added
Added
Updated
Updated
Updated
Updated
Updated
Added
Updated
Added
Added the last bullet ‘Application program interface (API)’ in

Section 8.4

Added
Added

Section 6.4: VCO calibration procedure

Ta b l e 1

.

Table 1: Pin description

.

Table 3: Operating conditions (refer to Figure 36: Typical

,

Table 5: Electrical specifications, Ta bl e 6 :

.

Section 5.8.2: VCO frequency calibration

Section 5.9: Output stage

.

Section 5.10: External VCO Buffer

FUNCTIONAL_MODE
Table 22: Bits at 00h and ST1

and

CALIBRATION

.

Section 6.3.2: Read-only register
Section 6.3.3: Default configuration
Section 6.4: VCO calibration procedure

Section 6.4.1: VCO calibration auto-restart feature

Section 7.4: VCO calibration procedure

Section 7.4.1: VCO calibration auto-restart feature

.

Note 4 on page 47
Figure 37, Figure 38

.

and

Figure 39

, pin #23 description

.

.

registers.

.

.

.

.

.

.

.

52/53

STW81102

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2008 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

53/53