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STW28NK60Z
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
N-CHANNEL 600 V - 0.155Ω - 27A TO-247
Zener-Protected SuperMESH™ MOSFET
Table 1: Ge neral Features
TYPE V
STW28NK60Z 600 V < 0.185 Ω 27 A 350 W
■ TYPICAL R
■ EXTREMELY HIGH dv/d t C APABILITY
■ 100% AVALANCHE TESTED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
DSS
(on) = 0.155 Ω
DS
R
DS(on)
I
P
D
W
REPEATIBILITY
DESCRIPTION
The SuperMESH™
series is obtained t hrough an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down , special
care is taken to ensure a very good dv/dt capability
for the most demanding app lication. Such series
complements ST full range of high vltage MOSFET s including revolutionary MSmesh™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-L INE POWER SUPPL IES
■ WELDING MACHINES
■ LIGHTING
Figure 1: Package
3
2
1
TO-247
Figure 2: Internal Schematic Diagram
Table 2: Order Codes
PART NUMBER MARKING PACKAGE PACKAGING
STW28NK60Z W28NK60Z TO-247 TUBE
Rev. 1
1/10November 2004
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STW28NK60Z
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
IDM(*)
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
T
stg
T
j
(*) Pulse wi dth limited by saf e operating ar ea
≤ 27 A, di/dt≤ 200 A/µs, VDD≤ V
(1) I
SD
Table 4: Thermal Data
Rthj-case Thermal Resistance Junction-case Max 0.36 °C/W
Rthj-amb
T
l
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 KΩ)
600 V
600 V
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C 27
Drain Current (continuous) at TC = 100°C
17 A
Drain Current (pulsed) 108 A
Total Dissipation at TC = 25°C
350 W
Derating Factor 2.77 W/°C
Gate source ESD (HBM-C = 100pF, R = 1.5 KΩ) 6000 V
Storage Temperature
Operating Junction Temperature
, TJ≤ T
(BR)DSS
JMAX
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
-55 to 150 °C
50
300
A
°C/W
°C
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
27 A
500 mJ
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Condition Min. Typ. Max Unit
BV
GSO
Gate-Source Breakdown
Igs= ± 1mA (Open Drain)
30 A
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specificall y been des igne d to enh ance not only the dev ice’s
ESD capability , but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to ach ieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diode s thus avoid the
usage of external components.
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STW28NK60Z
TABLE 7: ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 0 600 S
Voltage
I
I
V
GS(th)
R
DS(on
DSS
GSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125°C
DS
V
= ± 20 V ± 10 µA
GS
V
= VGS, ID = 150 µA 3
DS
3.75
1
50
4.5 V
VGS = 10 V, ID = 13.5 A 0.155 0.185 Ω
Resistance
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS = 15 V, ID = 13.5 A 26 S
g
fs
C
C
oss
C
t
d(on)
t
t
d(off)
t
Q
Q
Q
iss
rss
r
f
g
gs
gd
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 25 V, f = 1 MHz, VGS = 0 6350
V
DS
= 300 V, ID = 14 A,
V
DD
RG=4.7 Ω, V
GS
= 10 V
(Resistive Load see Figure 17))
= 480 V, ID = 28 A,
V
DD
VGS = 10 V
615
125
50
45
135
32
189
34
103
264 nC
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse durat ion = 300 µs, duty cycle 1.5 %.
(2) Pulse width limite d by safe operatin g area.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 27 A, VGS = 0
= 28 A, di/dt = 100 A/µs
I
SD
VDD = 35V, Tj = 25°C
(see test circuit Figure 5)
= 28 A, di/dt = 100 A/µs
I
SD
V
= 35V, Tj = 150°C
DD
(see test circuit Figure 5)
820
10
23.5
1020
14
27.5
27
108
1.6 V
A
A
ns
µC
A
ns
µC
A
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Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltag e
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 12: Capacitance Variations
Figure 13: Normal ized On R esistance vs Temperature
Figure 11: S ource-Drain Diode Forw ard Characteristics
Figure 14: Normalized BV
vs Temperature
DSS
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Figure 15: Maximum Avalanche Energy vs Temperature
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Figure 16: Unclamped Inductive Load Test Circuit
Figure 17: Switching Times Test Circuit For Resistive Load
Figure 19: Unclamped Inductive Wafeform
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
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TO-247 MECHANICAL DATA
DIM.
A 4.85 5.15 0.19 0.20
A1 2.20 2.60 0.086 0.102
b 1.0 1.40 0.039 0.055
b1 2.0 2.40 0.079 0.094
b2 3.0 3.40 0.118 0.134
c 0.40 0.80 0.015 0.03
D 19.85 20.15 0.781 0.793
E 15.45 15.75 0.608 0.620
e5.45 0.214
L 14.20 14.80 0.560 0.582
L1 3.70 4.30 0.14 0.17
L2 18.50 0.728
øP 3.55 3.65 0.140 0.143
øR 4.50 5.50 0.177 0.216
S5.50 0.216
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
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Table 10: Revision History
Date Revision Description of Change s
05-Nov-2004 1 First Release.
STW28NK60Z
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third parti es wh ic h m ay r esul t fr om its us e. No lic ens e is gr an ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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