Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has des igned an a dvanced family of power MOS FETs with outstanding
performances. The n ew patent pending strip l ay out
coupled with the Company’s proprieratyedge termination structure, gives the lowest RDS (on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteristics.
APPLICATIONS
■ SWITCH MODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
3
2
1
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt(1)Peak Diode Recovery voltage slope4V/ns
T
stg
T
(•)Pulse width limited by safe operating area
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
600V
600V
Gate- source Voltage±30V
Drain Current (continuos) at TC= 25°C
Drain Current (continuos) at TC= 100°C
()
Drain Current (pulsed)64A
Total Dissipation at TC= 25°C
16A
10A
220W
Derating Factor1.76W/°C
Storage Temperature–65 to 150°C
Max. Operating Junction Temperature150°C
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical compo nents in life support devices or systems without express written approval of STMicroelectronics.
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