This n-channel enhancement mode Power
MOSFET is the latest refinement of ST’s
STripFET™ process. The resulting transistor
shows extremely high packing density for low on
resistance, rugged avalanche characteristics and
low gate charge.
vs temperatureFigure 7.Static drain-source on resistance
VDSS
RDS(on)
(Ω)
VGS=10V
AM03163v1
2.5
2.0
1.5
1.0
6/12
0.5
100
0
200
300
400
I
D(A)
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Obsolete Product(s) - Obsolete Product(s)
STV200N55F3Electrical characteristics
Figure 8.Gate charge vs gate-source voltage Figure 9.Capacitance variations
Figure 10. Normalized gate threshold voltage
vs temperature
Figure 12. Source-drain diode forward
characteristics
Figure 11. Normalized on resistance vs
temperature
7/12
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Obsolete Product(s) - Obsolete Product(s)
Test circuitsSTV200N55F3
3 Test circuits
Figure 13. Switching times test circuit for
Figure 15. Test circuit for inductive load
resistive load
switching and diode recovery times
Figure 14. Gate charge test circuit
Figure 16. Unclamped inductive load test
circuit
Figure 17. Unclamped inductive waveformFigure 18. Switching time waveform
8/12
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STV200N55F3Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
9/12
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Package mechanical dataSTV200N55F3
PowerSO-10 mechanical data
Dim
mm
MinTypMax
A3.70
A10.000.10
A23.403.60
A31.251.35
b0.400.53
c0.350.55
D9.409.60
D17.407.60
E13.8014.40
E19.309.50
E27.207.60
E35.906.10
e1.27
L0.951.65
<0
o
8
o
0068039_E
10/12
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STV200N55F3Revision history
5 Revision history
Table 8.Document revision history
DateRevisionChanges
05-Mar-20081First release.
10-Nov-20082Document status promoted from preliminary to datasheet.
02-Mar-20093Figure 2 has been updated.
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STV200N55F3
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