Datasheet sts9d8nh3ll Datasheet

Page 1
Features
Type V
STS9D8NH3LL
low on-resistance STripFET™ Power MOSFET
DSSRDS(on)
30V < 0.022Ω 7nC 8A
Q
1
30V < 0.015Ω 8nC 9A
Q
2
STS9D8NH3LL
Dual N-channel 30 V - 0.012 Ω - 9 A - SO-8
Qg I
D
■ Optimal R
■ Conduction losses reduced
■ Switching losses reduced
DS
Application
■ Switching applications
Description
This device uses the latest advanced design rules of ST’s STrip based technology. The Q1 and Q2 transistors, show respectively, the best gate charge and on-resistance for minimizing the switching and conduction losses. This application specific Power MOSFET has been designed to replace two SO-8 packages in DC-DC converters.
S0-8
Figure 1. Internal schematic diagram
Table 1. Device summary
Order code Marking Package Packaging
STS9D8NH3LL 9D8H3LL- SO-8 Tape & reel
December 2007 Rev 3 1/14
www.st.com
14
Page 2
Contents STS9D8NH3LL
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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Page 3
STS9D8NH3LL Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings
Symbol Parameter Type Value Unit
V
V
I
DM
P
E
AS
1. Pulse width limited by safe operating area
2. Starting TJ = 25 °C, ID = 7.5 A
Drain-source voltage (vGS = 0)
DS
Gate- source voltage
GS
I
Drain current (continuous) at TC = 25°C
D
Drain current (continuous) at
I
D
TC = 100°C
(1)
Drain current (pulsed)
Total dissipation at TC = 25°C
TOT
(2)
Single pulse avalanche energy 150 mJ
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
30 30
±16 ±16
8 9
5
6.3
32 36
2 2
Table 3. Thermal data
Symbol Parameter Value Unit
(1)
R
thj-a
T
T
1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t < 10s
Thermal resistance junction-ambient max 62.5 °C/W
Thermal operating junction-ambient 150 °C
J
Storage temperature -55 to 150 °C
stg
V V
V V
A A
A A
A A
W W
3/14
Page 4
Electrical characteristics STS9D8NH3LL

2 Electrical characteristics

(T
Table 4. On/off states
=25°C unless otherwise specified)
CASE
Symbol Parameter Test conditions Type Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
R
DS(on)
Table 5. Dynamic
Drain-source Breakdown voltage
Zero gate voltage Drain current (V
Zero gate voltage Drain current (V
Gate-body leakage current (V
Gate threshold voltage
Static drain-source on resistance
Static drain-source on resistance
DS
= 0)
GS
GS
ID = 250 µA, VGS = 0
V
= Max rating
= 0)
= 0)
DS
=Max rating
V
DS
@125°C
V
= ± 16 V
GS
V
= VGS,
DS
= 250 µA
I
D
= 10 V, ID = 4 A
V
GS
= 10 V, ID = 4.5 A
V
GS
= 4.5 V, ID = 4 A
V
GS
= 4.5 V, ID = 4.5 A
V
GS
Q Q
Q Q
Q Q
Q Q
Q Q
Q Q
Q Q
30
1
30
2
1
2
1
2
1
2
1
1
1
2
1
2
1
2
0.018
0.012
0.020
0.014
1 1
10 10
±100 ±100nAnA
0.022
0.015ΩΩ
0.025
0.0175ΩΩ
V V
µA µA
µA µA
V V
Symbol Parameter Test conditions Type Min. Typ. Max. Unit
Q
C
C
C
Q
Q
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
Total gate charge
g
Gate-source charge
gs
= 25 V, f = 1 MHz,
V
DS
= 0
V
GS
= 15 V, ID = 8 A,
V
DD
= 4.5 V
V
GS
(see Figure 25)
Q
Gate-drain charge
gd
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
857
1070
147 290
20 34
7 8
2.5 2
2.3
2.8
10 11
pF pF
pF pF
pF pF
nC nC
nC nC
nC nC
4/14
Page 5
STS9D8NH3LL Electrical characteristics
Table 6. Switching times
Symbol Parameter Test conditions Type Min. Typ. Max. Unit
t
d(on)
Turn-on delay time
t
Rise time
r
t
d(off)
Turn-off delay time
t
Fall time
f
Table 7. Source drain diode
VDD=15 V, ID=4 A, RG=4.7 Ω,
= 4.5 V
V
GS
(see Figure 27)
=15 V, ID=4 A,
V
DD
=4.7 Ω,
R
G
VGS= 4.5V
(see Figure 27)
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
12
8.2
14.5
6
23
27.8
8
3.6
Symbol Parameter Test conditions Type Min Typ. Max Unit
V
=15 V, ID=4 A
DD
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Source-drain current
Source-drain current
(1)
(pulsed)
(2)
Forward on voltage ISD = 8 A, VGS = 0
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
R
G
V
GS
V
DD
R
G
V
GS
ISD = 8 A, V
DD
di/dt = 100 A/µs,
= 150°C
T
j
(see Figure 26)
=4.7 Ω,
=4.5 V
=15 V, ID= 4A
=4.7 Ω,
=4.5 V
= 15 V
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
Q
1
Q
2
15
22.8
5.7
14.9
0.76
1.3
8 9
32 36
1.5
1.5
ns ns ns ns
ns ns ns ns
A A
A A
V V
ns
ns nC nC
A A
5/14
Page 6
Electrical characteristics STS9D8NH3LL

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area for Q1 Figure 3. Safe operating area for Q2
Figure 4. Thermal impedance for Q1 Figure 5. Thermal impedance for Q2
Figure 6. Output characteristics for Q1 Figure 7. Output characteristics for Q2
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Page 7
STS9D8NH3LL Electrical characteristics
Figure 8. Transfer characteristics for Q1 Figure 9. Transfer characteristics for Q2
Figure 10. Static drain-source on resistance
Figure 12. Normalized BV
for Q1
for Q1
vs temperature
DSS
Figure 11. Static drain-source on resistance
for Q2
Figure 13. Normalized BV
vs temperature
DSS
for Q2
7/14
Page 8
Electrical characteristics STS9D8NH3LL
Figure 14. Gate charge vs gate-source voltage
for Q1
Figure 15. Gate charge vs gate-source voltage
for Q2
Figure 16. Capacitance variations for Q1 Figure 17. Capacitance variations for Q2
Figure 18. Normalized gate threshold voltage
8/14
vs temperature for Q1
Figure 19. Normalized gate threshold voltage
vs temperature for Q2
Page 9
STS9D8NH3LL Electrical characteristics
Figure 20. Normalized on resistance vs
temperature for Q1
Figure 22. Source-drain diode forward
characteristics for Q1
Figure 21. Normalized on resistance vs
temperature for Q2
Figure 23. Source-drain diode forward
characteristics for Q2
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Page 10
Test circuit STS9D8NH3LL

3 Test circuit

Figure 24. Switching times test circuit for
resistive load
Figure 26. Test circuit for inductive load
switching and diode recovery times
Figure 25. Gate charge test circuit
Figure 27. Unclamped Inductive load test
circuit
Figure 28. Unclamped inductive waveform Figure 29. Switching time waveform
10/14
Page 11
STS9D8NH3LL Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Page 12
Package mechanical data STS9D8NH3LL
SO-8 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.25 0.003 0.009
a2 1.65 0.064
a3 0.65 0.85 0.025 0.033
b 0.35 0.48 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.019
c1 45 (typ.)
D 4.8 5.0 0.188 0.196
E 5.8 6.2 0.228 0.244
e
e3 3.81 0.150
F 3.8 4.0 0.14 0.157
L 0.4 1.27 0.015 0.050
M 0.6 0.023
S 8 (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
1.27
0.050
12/14
Page 13
STS9D8NH3LL Revision history

5 Revision history

Table 8. Document revision history
Date Revision Changes
05-Jan-2007 1 First release
06-Mar-2007 2 Some value changed on Ta bl e 4 (R
10-Dec-2007 3 Added E
value on Table 2: Absolute maximum ratings
AS
DS(on)
for Q2)
13/14
Page 14
STS9D8NH3LL
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