This device uses the latest advanced design rules
of ST’s STrip based technology. The Q1 and Q2
transistors, show respectively, the best gate
charge and on-resistance for minimizing the
switching and conduction losses. This application
specific Power MOSFET has been designed to
replace two SO-8 packages in DC-DC converters.
Figure 2.Safe operating area for Q1Figure 3.Safe operating area for Q2
Figure 4.Thermal impedance for Q1Figure 5.Thermal impedance for Q2
Figure 6.Output characteristics for Q1Figure 7.Output characteristics for Q2
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Page 7
STS9D8NH3LLElectrical characteristics
Figure 8.Transfer characteristics for Q1Figure 9.Transfer characteristics for Q2
Figure 10. Static drain-source on resistance
Figure 12. Normalized BV
for Q1
for Q1
vs temperature
DSS
Figure 11. Static drain-source on resistance
for Q2
Figure 13. Normalized BV
vs temperature
DSS
for Q2
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Page 8
Electrical characteristicsSTS9D8NH3LL
Figure 14. Gate charge vs gate-source voltage
for Q1
Figure 15. Gate charge vs gate-source voltage
for Q2
Figure 16. Capacitance variations for Q1Figure 17. Capacitance variations for Q2
Figure 18. Normalized gate threshold voltage
8/14
vs temperature for Q1
Figure 19. Normalized gate threshold voltage
vs temperature for Q2
Page 9
STS9D8NH3LLElectrical characteristics
Figure 20. Normalized on resistance vs
temperature for Q1
Figure 22. Source-drain diode forward
characteristics for Q1
Figure 21. Normalized on resistance vs
temperature for Q2
Figure 23. Source-drain diode forward
characteristics for Q2
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Page 10
Test circuitSTS9D8NH3LL
3 Test circuit
Figure 24. Switching times test circuit for
resistive load
Figure 26. Test circuit for inductive load
switching and diode recovery times
Figure 25. Gate charge test circuit
Figure 27. Unclamped Inductive load test
circuit
Figure 28. Unclamped inductive waveformFigure 29. Switching time waveform
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Page 11
STS9D8NH3LLPackage mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/14
Page 12
Package mechanical dataSTS9D8NH3LL
SO-8 MECHANICAL DATA
DIM.
A1.750.068
a10.10.250.0030.009
a21.650.064
a30.650.850.0250.033
b0.350.480.0130.018
b10.190.250.0070.010
C0.250.50.0100.019
c145 (typ.)
D4.85.00.1880.196
E5.86.20.2280.244
e
e33.810.150
F3.84.00.140.157
L0.41.270.0150.050
M0.60.023
S8 (max.)
MIN.TYPMAX.MIN.TYP.MAX.
mm.inch
1.27
0.050
12/14
Page 13
STS9D8NH3LLRevision history
5 Revision history
Table 8.Document revision history
DateRevisionChanges
05-Jan-20071First release
06-Mar-20072Some value changed on Ta bl e 4 (R
10-Dec-20073Added E
value on Table 2: Absolute maximum ratings
AS
DS(on)
for Q2)
13/14
Page 14
STS9D8NH3LL
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