Datasheet sts3c2f100 Datasheet

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N-channel 100V - 0.110 Ω - 3A SO-8
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Complementary pair STripFET™ Power MOSFET
General features
Type V
STS3C2F100(N-channel) 100V <0.145 3.0A
STS3C2F100(P-channel) 100V <0.380 1.5A
■ Standard outline for easy automated surface
mount assembly
■ Ultra low on-resistance
Description
This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low on­resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
DSSRDS(on)ID
STS3C2F100
S0-8
Internal schematic diagram
Applications
■ Switching application
Order codes
Part number Marking Package Packaging
STS3C2F100 S3C2F100 SO-8 Tape & reel
November 2006 Rev 3 1/14
www.st.com
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Contents STS3C2F100
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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STS3C2F100 Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit
V
V
I
DM
P
T
1. Pulse width limited by safe operating area
Drain-source voltage (vgs = 0) 100 V
DS
Gate- source voltage ±20 V
GS
Drain current (continuos) at TC = 25°C 3.0 1.5 A
I
D
I
Drain current (continuos) at TC = 100°C 1.9 1.0 A
D
(1)
Drain current (pulsed) 12 6 A
Total dissipation at TC = 25°C 2 W
TOT
Storage temperature -55 to 150 °C
stg
Max. operating junction temperature 150 °C
T
j

Table 2. Thermal data

(1)
R
thj-a
1. When mounted on 1 in
Thermal resistance junction-ambient 62.5 °C/W
2
pad of 2 oz. copper, t ≤ 10 sec
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Electrical characteristics STS3C2F100

2 Electrical characteristics

(T

Table 3. On/off states

=25°C unless otherwise specified)
CASE
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source Breakdown voltage
S
Zero gate voltage Drain current (V
Gate-body leakage current (V
DS
= 0)
GS
= 0)
ID = 250 µA, VGS = 0
VDS = Max rating n-ch 1 µA
=Max rating,
V
DS
=125°C
T
C
V
= ±20V
GS
Gate threshold voltage VDS = VGS, ID = 250µA
= 10V, ID = 1.5A
Static drain-source on resistance
V
GS
= 10V, ID = 1.0A
V
GS
n-ch p-ch
100 V
p-ch 10 µA
n-ch p-ch
n-ch p-ch
n-ch p-ch
2V
0.110
0.320
±100 nA
0.145
0.380ΩΩ

Table 4. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit
(1)
g
fs
Forward transconductance
VDS = 20 V, ID= 1.5 A VDS = 30 V, ID= 1.0 A
n-ch p-ch
3 4
S S
C
C
C
Q
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
Total gate charge
g
VDS = 25V, f = 1 MHz,
= 0
V
GS
N-channel
VDD=80V ID=3A
=10V
V
Q
Q
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 .
Gate-source charge
gs
Gate-drain charge
gd
GS
P-channel
= 80V ID = 1.5A
V
DD
= 10V
V
GS
n-ch p-ch
n-ch p-ch
n-ch p-ch
n-ch p-ch
n-ch p-ch
n-ch p-ch
460 705
70 83
30 30
15 20
3.7
2.0
4.7
6.0
pF pF
pF pF
pF pF
2027nC
nC
nC nC
nC nC
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STS3C2F100 Electrical characteristics

Table 5. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit
N-channel
t
d(on)
Turn-on delay time
t
Rise time
r
= 50 V, ID = 1.5 A
V
DD
RG=4.7 Ω, VGS = 10 V
P-channel
= 50 V, ID = 1.5 A
V
DD
RG=4.7 Ω, VGS = 10 V
n-ch p-ch
n-ch p-ch
16 14
25 20
ns ns
ns ns
(see Figure 25)
N-channel
t
d(off)
Turn-off delay time
t
Fall time
f
VDD = 50 V, ID = 1.5 A
=4.7 Ω, VGS = 10 V
R
G
P-channel
= 50 V, ID = 1.5 A
V
DD
=4.7 Ω, VGS = 10 V
R
G
n-ch p-ch
n-ch p-ch
32 33
20
7.5
ns ns
ns ns
(see Figure 25)

Table 6. Source drain diode

Symbol Parameter Test conditions Min Typ. Max Unit
I
SDM
V
SD
I
Source-drain current
SD
Source-drain current
(1)
(pulsed)
(2)
Forward on voltage
ISD = 3A, VGS = 0
= 1.5A, VGS = 0
I
SD
N-channel
= 3 A, di/dt = 100A/µs
I
t
Q
I
RRM
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
SD
VDD=50 V, Tj =150 oC
P-channel
= 1.5 A, di/dt =
I
SD
100A/µs
=50 V, Tj =150 oC
V
DD
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
n-ch p-ch
n-ch p-ch
n-ch p-ch
n-ch p-ch n-ch p-ch n-ch p-ch
3.o
1.5AA
12
6.0AA
1.2
1.2VV
90
65 230 175
5.0
5.4
ns
ns nC nC
A A
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Electrical characteristics STS3C2F100

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area n-ch Figure 2. Thermal impedance n-ch
Figure 3. Output characterisics n-ch Figure 4. Transfer characteristics n-ch
Figure 5. Transconductance n-ch Figure 6. Static drain-source on resistance n-
ch
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STS3C2F100 Electrical characteristics
Figure 7. Gate charge vs gate-source voltage
n-ch
Figure 9. Normalized gate threshold voltage
vs temperature n-ch

Figure 8. Capacitance variations n-ch

Figure 10. Normalized on resistance vs
temperature n-ch
Figure 11. Source-drain diode forward
characteristics n-ch
Figure 12. Normalized breakdown voltage vs
temperature n-ch
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Electrical characteristics STS3C2F100

Figure 13. Safe operating area p-ch Figure 14. Thermal impedance p-ch

Figure 15. Output characterisics p-ch Figure 16. Transfer characteristics p-ch

Figure 17. Transconductance p-ch Figure 18. Static drain-source on resistance p-

ch
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STS3C2F100 Electrical characteristics
Figure 19. Gate charge vs gate-source voltage
p-ch
Figure 21. Normalized gate threshold voltage
vs temperature p-ch

Figure 20. Capacitance variations p-ch

Figure 22. Normalized on resistance vs
temperature p-ch
Figure 23. Source-drain diode forward
characteristics p-ch
Figure 24. Normalized breakdown voltage vs
temperature p-ch
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Test circuit STS3C2F100

3 Test circuit

Figure 25. Switching times test circuit for
Figure 27. Test circuit for inductive load
resistive load
switching and diode recovery times

Figure 26. Gate charge test circuit

Figure 28. Unclamped Inductive load test
circuit

Figure 29. Unclamped inductive waveform Figure 30. Switching time waveform

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STS3C2F100 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com
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Package mechanical data STS3C2F100
SO-8 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.25 0.003 0.009
a2 1.65 0.064
a3 0.65 0.85 0.025 0.033
b 0.35 0.48 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.019
c1 45 (typ.)
D 4.8 5.0 0.188 0.196
E 5.8 6.2 0.228 0.244
e
e3 3.81 0.150
F 3.8 4.0 0.14 0.157
L 0.4 1.27 0.015 0.050
M 0.6 0.023
S 8 (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
1.27
0.050
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STS3C2F100 Revision history

5 Revision history

Table 7. Revision history

Date Revision Changes
22-Jun-2004 1 First release
27-May-2005 2 New ECOPACK label
13-Nov-2006 3 The document has been reformatted
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STS3C2F100
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