Page 1
Dual N-channel 450 V, 3.2 Ω, 0.5 A SuperMESH3™
Features
Type V
DSS
R
STS1DN45K3 450 V < 3.8 Ω 0.5 A 1.7 W
■ 100% avalanche tested
■ Low input capacitances and gate charge
■ Low gate input resistance
Application
■ Switching applications
Description
SuperMESH3™ is a new Power MOSFET
technology that is obtained via improvements
applied to STMicroelectronics’ SuperMESH™
technology combined with a new optimized
vertical structure. The resulting product has an
extremely low on resistance, superior dynamic
performance and high avalanche capability,
making it especially suitable for the most
demanding applications.
DS(on)
max
I
D
P
w
STS1DN45K3
Power MOSFET in SO-8
Preliminary data
SO-8
Figure 1. Internal schematic diagram
Table 1. Device summary
Order codes Marking Packages Packaging
STS1DN45K3 1ll45 SO-8 Tape and reel
April 2010 Doc ID 17338 Rev 1 1/10
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
10
Page 2
Contents STS1DN45K3
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2/10 Doc ID 17338 Rev 1
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STS1DN45K3 Electrical ratings
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
Drain-source voltage (VGS = 0) 450 V
DS
Gate-source voltage ± 30 V
GS
Drain current (continuous) at TC = 25 °C 0.5 A
I
D
Drain current (continuous) at TC = 100 °C 0.32 A
I
D
(1)
Drain current (pulsed) 2 A
I
DM
V
V
Total dissipation at TC = 25 °C (dual operation) 1.7 W
P
TOT
I
AR
E
AS
dv/dt
T
stg
T
Total dissipation at T
Avalanche current, repetitive or not-repetitive (pulse
width limited by Tj max)
Single pulse avalanche energy
(starting Tj = 25°C, ID = IAR, VDD = 50 V)
(2)
Peak diode recovery voltage slope TBD V/ns
Storage temperature - 55 to 150 °C
Max. operating junction temperature 150 °C
j
= 25 °C (single operation) 1.3 W
C
0.5 A
TBD mJ
1. Pulse width limited by safe operating area
2. ISD ≤ 0.5 A, di/dt ≤ TBD A/µs, V
Table 3. Thermal data
Peak
< V
(BR)DSS
Symbol Parameter Value Unit
R
thj-amb
Thermal resistance junction-amb max
(single operation)
(1)
Thermal resistance junction-amb max
(dual operation)
62.5 °C/W
78 °C/W
1. When mounted on FR4 board (steady state)
Doc ID 17338 Rev 1 3/10
Page 4
Electrical characteristics STS1DN45K3
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4. On /off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
Gate-body leakage
current (V
DS
= 0)
= 0)
= 1 mA, VGS = 0 450 V
I
D
V
= Max rating
DS
= Max rating, TC=125 °C
V
DS
1
50µAµA
VGS = ± 20 V ±10 µA
Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V
Static drain-source on
resistance
V
= 10 V, ID = 0.5 A 3.2 3.8 Ω
GS
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
C
oss
C
C
o(tr)
Input capacitance
iss
Output capacitance
Reverse transfer
rss
capacitance
Equivalent
(1)
capacitance time
=25 V, f = 1 MHz,
V
DS
= 0
V
GS
related
= 0 to 360 V, VGS = 0
V
DS
C
o(er)
Equivalent
(2)
capacitance energy
related
R
Q
Q
Q
1. Time related is defined as a constant equivalent capacitance giving the same charging time as C
VDS increases from 0 to 80% V
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
when VDS increases from 0 to 80% V
Intrinsic gate
G
resistance
Total gate charge
g
Gate-source charge
gs
Gate-drain charge
gd
f = 1 MHz open drain - TBD - Ω
VDD = 360 V, ID = 0.5 A,
= 10 V
V
GS
(see Figure 3)
DSS
DSS
150
-
30
-
6
-TBD-pF
-TBD-pF
6
-
TBD
-
TBD
when
oss
oss
pF
pF
pF
nC
nC
nC
4/10 Doc ID 17338 Rev 1
Page 5
STS1DN45K3 Electrical characteristics
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max Unit
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off-delay time
t
Fall time
f
= 225 V, ID = 0.5 A,
V
DD
= 4.7 Ω, V
R
G
GS
(see Figure 4)
= 10 V
TBD
TBD
TBD
-
TBD
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
I
SDM
V
SD
Q
I
RRM
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Source-drain current
SD
(1)
Source-drain current (pulsed)
(2)
Forward on voltage ISD = 0.5 A, VGS = 0 - 1.6 V
t
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
Reverse recovery time
t
rr
Reverse recovery charge
rr
Reverse recovery current
ISD = 0.5 A, di/dt = 100 A/µs
= 100 V (see Figure 7)
V
DD
= 0.5 A, di/dt = 100 A/µs
I
SD
= 100 V, Tj = 150 °C
V
DD
(see Figure 7)
-
TBD
-
TBD
TBD
TBD
-
TBD
TBD
0.52A
ns
ns
ns
ns
A
ns
nC
A
ns
nC
A
Table 8. Gate-source Zener diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
BV
Gate-source breakdown
GSO
voltage
Igs=± 1 mA (open drain) 30 V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components
Doc ID 17338 Rev 1 5/10
Page 6
Test circuits STS1DN45K3
3 Test circuits
Figure 2. Switching times test circuit for
PW
resistive load
VGS
VD
RG
RL
D.U.T.
2200
µF
3.3
µF
AM01468v1
V
DD
Figure 4. Test circuit for inductive load
G
25
Ω
switching and diode recovery times
A
D
D.U. T.
S
B
R
FAST
DIODE
G
A
A
L=100µH
B
B
D
G
S
3.3
µF
1000
µF
V
DD
Figure 3. Gate charge test circuit
V
i=20V=VGMAX
PW
2200
µF
1kΩ
12V
IG=CONST
2.7kΩ
47kΩ
47kΩ
100Ω
100nF
D.U.T.
AM01469v1
Figure 5. Unclamped inductive load test
circuit
L
VD
ID
Vi
D.U. T.
2200
µF
3.3
µF
1kΩ
VDD
V
VDD
G
Pw
AM01470v1
Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform
V(BR)DSS
VD
IDM
ID
VDD
VDD
AM01472v1
0
0
10%
tdon
ton
90%
tr
10%
V
GS
6/10 Doc ID 17338 Rev 1
VDS
90%
tdoff
AM01471v1
toff
tf
90%
10%
AM01473v1
Page 7
STS1DN45K3 Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Doc ID 17338 Rev 1 7/10
Page 8
Package mechanical data STS1DN45K3
SO-8 mechanical data
Dim.
Min. Typ. Max.
mm
A 1.75
A1 0.10 0.25
A2 1.25
b 0.28 0.48
c0.17 0.23
D4.804.90 5.00
E5.80 6.00 6.20
E1 3.80 3.90 4.00
e1.27
h0.25 0.50
L0.40 1.27
L1 1.04
k0° 8°
ccc 0.10
8/10 Doc ID 17338 Rev 1
0016023_D
Page 9
STS1DN45K3 Revision history
5 Revision history
Table 9. Document revision history
Date Revision Changes
07-Apr-2010 1 First release
Doc ID 17338 Rev 1 9/10
Page 10
STS1DN45K3
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10/10 Doc ID 17338 Rev 1
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