This N-channel Power MOSFET is developed with
STMicroelectronics unique STripFET
has specifically been designed to sustain high
TID and provide immunity to heavy ion effects.
Table 1.Device summary
Order code
STRH8N10N1-
STRH8N10NGTBDESCC flightTarget
ESCC part
number
Note:Contact ST sales office for information about the specific conditions for product in die form
4. Not tested in production, guaranteed by process.
Source-drain current
SD
(2)
Source-drain current (pulsed)
(3)
Forward on voltage
(4)
Reverse recovery time
(4)
Reverse recovery charge
rr
(4)
Reverse recovery current
(4)
Reverse recovery time
(4)
Reverse recovery charge
rr
(4)
Reverse recovery current
= 8 A, VGS = 0
I
SD
= 8 A, VGS = 0,
I
SD
TC = 125 °C
= 8 A, di/dt = 100
I
SD
A/µs
= 17 V, Tj = 25 °C
V
DD
= 8 A,
I
SD
di/dt = 100 A/µs, VDD=
17 V, Tj = 150 °C
196245
1.2
10
282352
1.7
10.5
6
24
1.5
1.275
294ns
422ns
ns
ns
ns
ns
A
A
V
µC
A
µC
A
6/18Doc ID 010029 Rev 2
Page 7
STRH8N10Radiation characteristics
3 Radiation characteristics
The technology of the STMicroelectronics rad-hard Power MOSFETs is extremely resistant
to radiative environments. Every manufacturing lot is tested for total ionizing dose, according
to the ESCC 22900 specification window 1, using the TO-39 package. Both pre-irradiation
and post-irradiation performances are tested and specified using the same circuitry and test
conditions in order to provide a direct comparison.
(T
= 22 ± 3 °C unless otherwise specified).
amb
Total dose radiation (TID) testing
One bias conditions using the TO-39 package:
–V
The following parameters are measured (see Table 9, Table 10 and Table 11):
●before irradiation
●after irradiation
●after 24 hrs @ room temperature
●after 168 hrs @ 100 °C anneal
bias: + 15 V applied and VDS= 0 V during irradiation
The technology of the STMicroelectronics rad-hard Power MOSFETs is extremely resistant
to heavy ion environment for single event effect according to MIL-STD-750E method 1080
(bias circuit in Figure 3: Single event effect, bias circuit) SEB and SEGR tests have been
performed with a fluence of 3e+5 ions/cm².
The accept/reject criteria are:
●SEB test: drain voltage checked, trigger level is set to V
soon as a SEB occurs or if the fluence reaches 3e+5 ions/cm².
●SEGR test: the gate current is monitored every 100 ms. A gate stress is performed
before and after irradiation. Stop condition: as soon as the gate current reaches 100 nA
(during irradiation or during PIGS test) or if the fluence reaches 3e+5 ions/cm².
The results are:
–no SEB
–SEGR test produces the following SOA (see Table 12: Single event effect (SEE),
safe operating area (SOA) and Figure 2: Single event effect, SOA)
= - 5 V. Stop condition: as
ds
Table 12.Single event effect (SEE), safe operating area (SOA)
V
(V)
Energy
Ion
Let (Mev/(mg/cm
Kr327689410080603010
2
)
(MeV)
Range
(µm)
@V
=0 @VGS= -2 V @VGS= -5 V @VGS= -10 V @VGS= -20 V
GS
DS
8/18Doc ID 010029 Rev 2
Page 9
STRH8N10Radiation characteristics
Figure 2.Single event effect, SOA
100
Kr (32 MeV .cm²/mg)
-20-15-10-50
Vgs (V)
Figure 3.Single event effect, bias circuit
(a)
90
80
70
60
50
40
30
20
10
0
Vds (% Vdsmax)
a. Bias condition during radiation refer to Table 12: Single event effect (SEE), safe operating area (SOA) .
Figure 8.Gate charge vs gate-source voltage Figure 9.Capacitance variations
V
GS
10
(V)
V
DS
= 50 V
I
D
20
= 8 A
V
DS
(V)
HV33210
12
0.1
3.504.004.505.005.506.00
C
(pF)
1000
10
8
D
= 4 A
I
100
6
4
I
D
= 2 A
10
2
0
0
10
5
15
20
Q
g
(nC)
1
0.1
1
10
VGS(V)
Ciss
Coss
Crss
V
HV33220
DS
(V)
10/18Doc ID 010029 Rev 2
Page 11
STRH8N10Electrical characteristics (curves)
Figure 10. Normalized BV
vs temperatureFigure 11. Static drain-source on resistance
DSS
Figure 12. Normalized gate threshold voltage
vs temperature
R
DS(on)
(mΩ)
800
VGS=12 V
700
600
500
400
300
200
100
0
13
24
567
I
Figure 13. Normalized on resistance vs
temperature
D
(A)
HV33240
Figure 14. Source drain-diode forward
characteristics
V
SD
(V)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1
2
j =
-50 °C
T
T
j =
25 °C
T
j =
150 °C
4
3
6
5
7
HV33270
I
SD
(A)
Doc ID 010029 Rev 211/18
Page 12
Test circuitSTRH8N10
5 Test circuit
Figure 15. Switching times test circuit for resistive load
1. Max driver V
Figure 16. Source drain diode
slope = 1V/ns (no DUT)
GS
(1)
12/18Doc ID 010029 Rev 2
Page 13
STRH8N10Test circuit
Figure 17. Unclamped inductive load test circuit (single pulse and repetitive)
Doc ID 010029 Rev 213/18
Page 14
Package mechanical dataSTRH8N10
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
14/18Doc ID 010029 Rev 2
Page 15
STRH8N10Package mechanical data
Table 13.TO-39 mechanical data
mmInch
Dim.
Min.Typ.Max.Min.Typ.Max.
A12.70
B0.400.490.0160.019
C0.580.740.0230.029
D6.006.400.2370.252
E8.158.250.3580.362
F9.109.200.3580.362
G4.935.230.1940.206
H0.850.950.0330.037
I0.750.850.0290.033
L42°48°
Figure 18. TO-39 drawing
14.200.500
-
-
0.559
Doc ID 010029 Rev 215/18
Page 16
Order codesSTRH8N10
7 Order codes
Table 14.Ordering information
Order code
STRH8N10N1-
STRH8N10NGTBDESCC flight TargetTBD
ESCC part
number
Quality
level
Engineering
model
EPPL Package
TO-39Gold
Lead
finish
MarkingPacking
STRH8N10N1
Strip
pack
Contact ST sales office for information about the specific conditions for products in die form
and other package options.
16/18Doc ID 010029 Rev 2
Page 17
STRH8N10Revision history
8 Revision history
Table 15.Document revision history
DateRevisionChanges
20-May-20111First release.
09-Nov-20112
Updated dynamic values on Table 6: Dynamic, Table 7: Switching
times.
Doc ID 010029 Rev 217/18
Page 18
STRH8N10
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