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STP8NM50
STP8NM50FP
N-CHANNEL 500V - 0.7Ω - 8A TO-220/TO-220FP
MDmesh™Power MOSFET
TYPE V
STP8NM50
STP8NM50F P
n
TYPICAL RDS(on) = 0.7Ω
n
HIGH dv/dt AND AVALANCHE CAPABILITIES
n
100% AVALANCHE TESTED
n
LOW INPUT CAPACITANCE AND GATE
DSS
500V
500V
R
DS(on)
< 0.8Ω
< 0.8Ω
I
D
8 A
8 A
CHARGE
n
LOW GATE INPUT RESIST ANC E
DESCRIPTION
The MDmesh™
is a new revolutionary MOSFET
technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar competition’s products.
APPLICATIONS
The MDmesh™ family is very suitable for increasing
power density of high voltage converters allowing
system miniaturization and higher efficiencies.
3
2
1
1
TO-220 TO-220FP
INTERNAL SCHEMATIC DIAGRAM
3
2
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
STP8NM50 STP8NM50FP
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt Peak Diode Recovery voltage slope 15 V/ns
V
ISO
T
stg
T
j
(•)Pu l se width limited by safe oper ating area
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage ±30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
(l)
Drain Current (pulsed) 20 20 (*) A
Total Dissipation at TC = 25°C
Derating Factor 0.4 W/°C
Insulation Winthstand Voltage (DC) -- 2500 V
Storage Temperature
Max. Operating Junction Temperature
(*)Lim i ted only by maxim um temper at ure allowed
3.1 3.1 (*) A
120 30 W
500 V
500 V
5 5 (*) A
–65 to 150 °C
1/9August 2002
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STP8NM50/STP8NM50FP
THERMA L D ATA
TO-220 / I²PAK TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1.04 4.21 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Par amet er Max Value Unit
I
AR
E
AS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
2.5 A
200 mJ
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS OTHERWISE SPECIFIED)
CASE
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID = 250 µA, VGS = 0 500 V
Breakdown Voltage
ON
I
I
GSS
(1)
DSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±30V ±100 nA
GS
1µA
10 µA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS, ID = 250µA
DS
VGS = 10V, ID = 2.5A
345V
0.7 0.8 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 88 pF
Reverse Transfer
Capacitance
C
(2) Equivalent Output
oss eq.
Capacitance
R
G
1. Pulsed: Pu l se duration = 300 µs, duty cyc l e 1.5 %.
2. C
Gate Input Resistance f=1 MHz Gate DC Bias = 0
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
V
.
DSS
ID= 2.5A
V
DS
VGS = 0V, VDS = 0V to 400V 50 pF
Test Signal Level = 20mV
Open Drain
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
2.4 S
415 pF
12 pF
3 Ω
when VDS increase s fr om 0 to 80%
oss
2/9
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STP8NM50/STP8NM50F P
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
gs
gd
Turn-on Delay Time
Rise Time 8 ns
Total Gate Charge
g
Gate-Source Charge 4 nC
Gate-Drain Charge 6 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
t
f
c
Off-voltage Rise Time
Fall Time 6 ns
Cross-over Time 13 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µ s, duty cycle 1.5 %.
2. Pulse width lim i t ed by safe operating area.
3. Pulse width lim i t ed by safe operating area.
(2)
Source-drain Current 5 A
Source-drain Current (pulsed) 20 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charg e
Reverse Recovery Charg e
Reverse Recovery Time
Reverse Recovery Charg e
Reverse Recovery Charg e
= 250V, ID = 2.5A
DD
RG= 4.7Ω VGS = 10V
(see test circuit, Figure 3)
V
= 400V, ID = 5A,
DD
V
= 10V
GS
V
= 400V, ID = 5A,
DD
RG= 4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
ISD = 5A, VGS = 0
= 5A, di/dt = 100A/µs,
I
SD
VDD = 100 V, Tj = 25°C
(see test circuit, Figure 5)
= 5A, di/dt = 100A/µs,
I
SD
V
= 100 V, Tj = 150°C
DD
(see test circuit, Figure 5)
16 ns
13 nC
14 ns
1.5 V
185
1.1
11.5
270
1.6
12
ns
µC
A
ns
µC
A
Safe Operating Area For TO-220FPSafe Operating Area For TO-220
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STP8NM50/STP8NM50FP
Thermal Impedance For TO-220 Thermal Impedance For TO-220FP
Output Characteristics
Transconductance
Transfer Characteristics
Static Drain-source On Resistance
4/9
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STP8NM50/STP8NM50F P
Capacitance VariationsGate Charge vs Gate-source Voltage
Normalized Gate Threshold Volta ge vs Temp.
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
5/9
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STP8NM50/STP8NM50FP
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
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E
TO-220 MECHANICAL DATA
STP8NM50/STP8NM50F P
DIM.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A
C
D
L5
Dia.
L7
D1
L6
L2
L9
F1
G1
F
H2
G
F2
L4
P011C
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STP8NM50/STP8NM50FP
TO-220FP MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 0.385 0.417
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
mm inch
E
A
D
8/9
B
L3
L6
L7
¯
F1
F
G1
H
G
F2
123
L2
L4
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STP8NM50/STP8NM50F P
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the
consequences of use of su ch in formation nor for any in fringement of patents or other rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.
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