Page 1
STP80PF55
P-CHANNEL 55V - 0.016 Ω - 80A TO -220
STripFET™ II POWER MOSFET
PRELIMINARY DATA
TYPE
V
DSS
STB80PF55 55 V < 0.018
■ TYPICAL R
■ EXCEPTIONA L dv/d t CAPABILITY
■ 100% AVALANCHE TESTED
■ APPLICATION ORIENTED
(on) = 0.016 Ω
DS
R
DS(on)
I
D
80 A
Ω
CHARACTERIZATION
DESCRIPTION
This Power MOSFET is the latest dev elo pment of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ MOTOR CONTROL
■ DC-DC & DC-AC CONVERTERS
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
(*) Drain Current (continuos) at T
I
D
I
D
(
I
DM
P
tot
dv/dt
E
AS
T
stg
T
j
(
Pulse widt h l i m i ted by safe op erating area
•)
(*) Curren t Lim i ted by Package
February 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
55 V
55 V
Gate- source Voltage ± 16 V
= 25°C
C
Drain Current (continuos) at TC = 100°C
•)
Drain Current (pulsed) 320 A
Total Dissipation at TC = 25°C
80 A
57 A
300 W
Derating Factor 2 W/°C
(1)
Peak Diode Recovery voltage slope 7 V/ns
(2)
Single Pulse Avalanche Energy 1.4 mJ
Storage Temperature
Max. Operating Junction Temperature
Note: F or t he P- CHAN NEL MOS FE T ac tu al po la rity o f v olt ages a nd
current has to be rever sed
≤ 40A, di/dt ≤ 300A/µs , VDD ≤ V
(1) I
SD
(2) Starting Tj = 25 oC, ID = 80A, VDD = 40V
-55 to 175 °C
(BR)DSS
, Tj ≤ T
JMAX.
1/6
Page 2
STP80PF55
THERMA L D ATA
Rthj-case
Rthj-amb
T
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
l
Max
Max
Typ
0.5
62.5
300
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C unless otherwise specified)
case
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
V
(BR)DSS
Drain-source
= 250 µA, VGS = 0
D
55 V
Breakdown Voltage
V
= Max Rating
DS
V
= Max Rating TC = 125°C
DS
V
= ± 16 V
GS
1
10
±100 nA
ON
(*)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS ID = 250 µA
DS
V
= 10 V ID = 40 A
GS
234V
0.016 0.018
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
> I
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
I
D
V
DS
= 40 A
x R
D(on)
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
32 S
5500
1130
600
µA
µA
Ω
pF
pF
pF
2/6
Page 3
STP80PF55
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Q
g
Q
gs
Q
gd
(*)
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 25 V ID = 40 A
V
DD
R
= 4.7 Ω VGS = 10 V
G
(Resistive Load, Figure 3)
= 25 V ID = 80 A VGS= 10V
V
DD
35
190
190
27
65
258 nC
ns
ns
nC
nC
SWITCHING OFF
(*)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
Turn-off Delay Time
t
f
Fall Time
V
DD
R
= 4.7 Ω V
G
GS
= 10 V
165
80
= 25 V ID = 40 A
(Resistive Load, Figure 3)
t
r(Voff)
t
t
f
c
Off-voltage Rise Time
Fall Time
Cross-over Time
SOURCE DRAIN DIODE
(*)
= 40 V ID = 80 A
V
clamp
R
= 4.7 Ω V
G
GS
= 10 V
(Inductive Load, Figure 5)
60
40
85
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulse width [ 300 µs, duty cycle 1.5 %.
(
•)
Pulse width limited by T
Source-drain Current
(•)
Source-drain Current (pulsed)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
JMAX
I
= 80 A VGS = 0
SD
= 80 A di/dt = 100A/µs
I
SD
V
= 25 V Tj = 150°C
DD
(see test circuit, Figure 5)
80
320
1.3 V
110
495
9
ns
ns
ns
ns
ns
A
A
ns
nC
A
3/6
Page 4
STP80PF55
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
4/6
Page 5
E
TO-220 MECHANICAL DATA
STP80PF55
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
mm inch
A
C
D
D1
L2
F1
L5
Dia.
G1
F
F2
L9
G
H2
L7
L6
L4
P011C
5/6
Page 6
STP80PF55
Information furnished is believed to be ac curate and reli able. Howev er, STMicroel ectronics assumes no responsibilit y for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.
The ST log o i s registered trademark of STMicroelectronics
2002 STMi croelectr oni cs - All Rights Reserved
All other names are the property of their respective owners.
Australi a - Brazil - Canada - Chin a - F i nl and - Franc e - Germany - Hong Kong - Ind i a - Is rael - Ital y - J apan - Malaysia - Malt a - Morocco -
Singapor e - S pai n - Sweden - Swi tzerland - United Kingdom - United S tates.
STMicroelect ro n ics GRO UP OF COMPANI ES
http://www.st.com
6/6
Loading...