Datasheet stp75nf68 Datasheet

Page 1
Features
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R
Type V
STP75NF68 68 V < 0.014 Ω 80 A
■ Exceptional dv/dt capability
■ 100% avalanche tested
DSS
DS(on)
max
■ Switching applications
Description
STP75NF68
N-channel 68 V, 0.010 Ω, 80 A, TO-220
STripFET™ II Power MOSFET
I
D
3
2
1
TO-220
This Power MOSFET series realized with STMicroelectronics unique STripFET™ process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable in advanced high-efficiency switching applications.

Table 1. Device summary

Order code Marking Package Packaging
STP75NF68 75NF68 TO-220 Tube

Figure 1. Internal schematic diagram

August 2008 Rev 2 1/12
www.st.com
12
Page 2
Contents STP75NF68
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/12
Page 3
STP75NF68 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit
I
V
V
DM
P
Drain-source voltage (VGS = 0) 68 V
DS
Gate-source voltage ± 20 V
GS
Drain current (continuous) at TC = 25 °C 80 A
I
D
I
Drain current (continuous) at TC=100 °C 56 A
D
(1)
Drain current (pulsed) 320 A
Total dissipation at TC = 25 °C 190 W
TOT
Derating factor 1.27 W/°C
(2)
dv/dt
E
AS
T
1. Pulse width limited by safe operating area
2. ISD ≤ 80 A, di/dt ≤ 300 A/µs, VDD ≤ V
3. Starting TJ = 25 oC, ID = 40 A, VDD = 34 V
Peak diode recovery voltage slope 13 V/ns
(3)
Single pulse avalanche energy 700 mJ
Storage temperature -55 to 175 °C
stg
T
Operating junction temperature 175 °C
J
, TJ ≤ T
(BR)DSS
JMAX

Table 3. Thermal data

Symbol Parameter Value Unit
R
thj-case
R
thj-amb
T
1. 1.6mm from case for 10 sec
Thermal resistance junction-case max 0.79 °C/W
Thermal resistance junction-ambient max 62.5 °C/W
Maximum lead temperature for soldering
l
purpose
(1)
300 °C
3/12
Page 4
Electrical characteristics STP75NF68

2 Electrical characteristics

(T
=25°C unless otherwise specified)
CASE

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown voltage
Zero gate voltage drain current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
Gate threshold voltage
Static drain-source on resistance
= 250 µA, VGS= 0
I
D
V
= Max rating,
DS
V
= Max rating @125 °C
DS
= ±20 V
V
GS
= VGS, ID = 250 µA
V
DS
VGS= 10 V, ID= 40 A
68 V
1
10µAµA
±100 nA
23 4V
0.010 0.014 Ω

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit
(1)
g
fs
C
C
C
Q
Q
Q
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
Forward transconductance
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
g
Total gate charge Gate-source charge
gs
Gate-drain charge
gd
V
= 15 V, ID = 40 A
DS
=25 V, f = 1 MHz,
V
DS
V
= 0
GS
VDD = 34 V, ID = 80 A
=10 V
V
GS
60 S
2550
550 175
75 17 30
pF pF pF
nC nC nC
4/12
Page 5
STP75NF68 Electrical characteristics

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off delay time Fall time
t
f
= 34 V, ID= 40 A,
V
DD
=4.7 Ω, VGS=10 V
R
G
Figure 13 on page 8
17 60 90 75
ns ns ns ns

Table 7. Source drain diode

Symbol Parameter Test conditions Min Typ. Max Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Source-drain current 80 A
(1)
Source-drain current (pulsed) 320 A
(2)
Forward on voltage
rr
Reverse recovery time Reverse recovery charge
rr
Reverse recovery current
I
I
SD
SD
= 80 A, V
= 80 A,
GS
= 0
di/dt = 100 A/µs,
= 25 V, TJ = 150 °C
V
DD
Figure 15 on page 8
70
160
4.7
1.5 V
ns µC
A
5/12
Page 6
Electrical characteristics STP75NF68

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance
I
D
AM00935v1
(A)
Operation in this area is limited by max R
DS(on)
100
100µs
10
1ms
10ms
1
0.1
0.1
1
10
V
DS
(V)
Figure 4. Output characteristics Figure 5. Transfer characteristics
I
D
(A)
250
VGS=10V
8V
200
7V
AM00936v1
I
D
(A)
250
200
VDS=15V
AM00937v1
150
100
6V
50
5V
0
0
Figure 6. Normalized BV
V
BR(DSS)
(norm)
5
GS
V
D
=250µA
I
=0
10
DSS
15
V
DS
(V)
vs temperature Figure 7. Static drain-source on resistance
AM00957v1
1.2
1.1
1.0
0.9
0.8
-50
0
50
100
T
J
(°C)
R
150
100
50
DS(on)
(Ω)
10.5
10
9.5
8.5
0
1
0
3 4
2
5
7
6
V
GS
(V)
AM00951v1
9
8
20
0
40
60
80
I
D
(A)
6/12
Page 7
STP75NF68 Electrical characteristics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
V
GS
AM00952v1
(V)
12
VDD=34V
I
D
=80A
10
8
6
4
2
0
20
0
40
60
80
Q
g
(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
V
GS(th)
(norm)
1.0
0.9
VDS=V
GS
ID=250µA
AM00954v1
C(pF)
TJ=25°C
5000
f=1MHz
4000
3000
Ciss
2000
Crss
1000
0
0
10
20
30
40 50 60
Coss
Figure 11. Normalized on resistance vs
temperature
R
DS(on)
(norm)
1.8
1.4
VGS=10V
D
=40A
I
AM00953v1
Q
g
(nC)
AM00955v1
0.8
0.7
0.6
-50
0
50
100
T
J
(°C)
Figure 12. Source-drain diode forward
characteristics
V
SD
(V)
1.1
0.9
0.7
0.5 175°C
0.3 0
20
T
J
=-55°C
40
25°C
60
80
AM00956v1
I
SD
(A)
1.0
0.6
0.2
-50
100
T
J
0
50
(°C)
7/12
Page 8
Test circuits STP75NF68

3 Test circuits

Figure 13. Switching times test circuit for
resistive load
Figure 15. Test circuit for inductive load
switching and diode recovery times

Figure 14. Gate charge test circuit

Figure 16. Unclamped inductive load test
circuit

Figure 17. Unclamped inductive waveform

8/12
Page 9
STP75NF68 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
9/12
Page 10
Package mechanical data STP75NF68
TO-220 mechanical data
Dim
Min Typ Max Min Typ Max
mm inch
A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034
b1 1.14 1.70 0.044 0.066
c0.49 0.70 0.019 0.027
D 15.25 15.75 0.6 0.62
D1 1.27 0.050
E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F1.23 1.32 0.048 0.051
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L3028.90 1.137
∅P 3.75 3.85 0.147 0.151
Q2.65 2.95 0.104 0.116
10/12
Page 11
STP75NF68 Revision history

5 Revision history

Table 8. Document revision history

Date Revision Changes
24-Jul-2008 1 First release
06-Aug-2008 2 Document status promoted from preliminary data to datasheet
11/12
Page 12
STP75NF68
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