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STP6NS25
N-CHANNEL 250V - 0.9Ω -6ATO-220
MESH O VERL AY™ MOSFET
TYPE V
DSS
R
DS(on)
I
D
STP6NS25 250 V < 1.1 Ω 6A
■ TYPICAL R
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
(on) = 0.9 Ω
DS
DESCRIPTION
Using the l ate st high voltage MESH OVERLAY™
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding
performance. The new patented STrip layout coupled with the Company’s proprietary ed ge termination structure, makes it suitable in coverters for
lighting applications.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLIES (SMPS)
■ DC-DC CONVE RTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAX IMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt (1) Peak Diode Recovery voltage slope 5 V/ns
T
stg
T
j
(•)Pulse width limited by safe operating area
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
250 V
250 V
Gate- source Voltage ± 20 V
Drain Current (continuos) at TC= 25°C
Drain Current (continuos) at TC= 100°C
()
Drain Current (pulsed) 24 A
Total Dissipation at TC= 25°C
6A
4A
70 W
Derating Factor 0.56 W/°C
Storage Temperature –65 to 150 °C
Max. Operating Junction Temperature 150 °C
(1) ISD≤ 6A, di/dt≤300 A/µs, VDD≤ V
(BR)DSS
,Tj≤T
jMAX
1/8November 2002
Page 2
STP6NS25
THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 1.79 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTE RISTICS (TCASE = 25 °C UNLE SS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
Drain-source
= 25 °C, ID=IAR,VDD=50V)
j
ID= 250 µA, VGS= 0 250 V
4A
75 mJ
Breakdown Voltage
= Max Rating
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
=0)
=0)
V
DS
= Max Rating, TC= 125 °C
V
DS
V
= ±20V ±100 nA
GS
1µA
50 µA
ON (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
V
DS=VGS,ID
VGS=10V,ID=2A
= 250µA
234V
0.9 1.1 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS>I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 64 pF
Reverse Transfer
Capacitance
D(on)xRDS(on)max,
ID=2A
V
=25V,f=1MHz,VGS=0
DS
1 3.5 S
355 pF
30 pF
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STP6NS25
ELECTRICAL CHARACTE RISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 18 ns
Total Gate Charge
Gate-Source Charge 3.2 nC
Gate-Drain Charge 7.5 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(Voff)
t
t
r(Voff)
t
t
f
f
c
Turn-off- Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
SOURCE DR AIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Source-drain Current 6 A
(2)
Source-drain Current (pulsed) 24 A
(1)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge 0.5 µC
Reverse Recovery Current 7 A
=125V,ID=3A
DD
R
= 4.7Ω VGS=10V
G
(see test circuit, Figure 3)
V
=200V,ID=4A,
DD
=10V
V
GS
VDD= 125V, ID=2A,
RG=4.7Ω, VGS= 10V
(see test circuit, Figure 3)
= 200V, ID=4A,
V
clamp
RG=4.7Ω, VGS= 10V
(see test circuit, Figure 5)
ISD= 6 A, VGS=0
I
= 6 A, di/dt = 100A/µs
SD
V
=30V,Tj= 150°C
DD
(see test circuit, Figure 5)
12 ns
19 27 nC
70
10
13
10
21
1.5 V
124 ns
ns
ns
ns
ns
ns
Thermal ImpedanceSafe Operating Area
3/8
Page 4
STP6NS25
Output Characteristics
Transconductance
Transfer Characteristics
Static Drain-source On Resistance
Gate Char ge vs Gate-sourc e Voltage
4/8
Capacitance Variations
Page 5
Source-drain Diode Forward Characteristics
STP6NS25
Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.
5/8
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STP6NS25
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery T imes
Fig. 4: Gate Charge test Circuit
6/8
Page 7
E
TO-220 MECHANICAL DATA
P011C
STP6NS25
DIM.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A
C
D
L5
Dia.
L7
D1
L6
L2
L9
F1
G1
F
H2
G
F2
L4
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STP6NS25
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of su ch in formation nor for any in fringement of patents or other rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.
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© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
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