Page 1
N - CHANNEL CLAMPED 10mΩ - 60A - TO-220
FULLY PROTECTED MESH OVERLAY MOSFET
TYPE V
DSS
ST P60NS04Z CLAMP ED <0.015 Ω 60 A
■ TYPICALR
■ 100%AVALANCHETESTED
■ LOW CAPACITANCEAND GATECHARGE
■ 175
o
C MAXIMUMJUNCTION
DS(on)
= 0.010 Ω
TEMPERATURE
R
DS(on)
I
D
STP60NS04Z
PRELIMINARY DATA
DESCRIPTION
This fully clamped Mosfet is produced by using
3
2
1
the latest advanced Company’s Mesh Overlay
processwhich is based on a novelstrip layout.
TO-220
The inherent benefits of the new technology
coupledwith the extra clampingcapabilities make
this product particularly suitable for the harshest
operation conditions such as those encountered
in the automotive environment. Any other
INTERNAL SCHEMATIC DIAGRAM
application requiring extra ruggedness is also
recommended.
APPLICATIONS
■ ABS, SOLENOIDDRIVERS
■ MOTORCONTROL
■ DC-DCCONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
I
DM
P
V
ESD
V
ESD
V
ESD
T
(•) Pulse width limited by safe operating area (1)ISD≤60 A, di/dt ≤ 300 A/µs, VDD≤ V
December 1999
Dra in- sour c e Volta ge (VGS= 0) CLAMPED V
DS
Drain- gate Voltage CLAMPED V
DG
Gate-s ource Voltage CLAMPED V
GS
Dra in Cu rr ent (conti nuous) at Tc=25oC60A
I
D
Dra in Cu rr ent (conti nuous) at Tc= 100oC42A
I
D
Dra in Gate Curre nt (co nt inuous)
DG
Gat e Sourc e Current (cont inuous) ± 50 mA
GS
50 mA
±
(•) Dra in Cu rr ent (pulsed) 240 A
Tot al Dissipatio n at Tc=25oC 140 W
tot
Der ati ng Fa c t or 0.93 W/
Gat e- Source ESD (HBM - C= 100pF, R=1.5 kΩ)2kV
(G-S)
(G-D) Gate-Drain ES D (HBM - C = 100pF, R=1. 5 kΩ)4kV
(D-S) Drain-Source ESD (HB M - C= 100pF, R=1. 5 kΩ)4kV
St orage Tempe rat ure -65 to 175
stg
Max. Operating Jun ct ion Temperatur e -40 to 175
T
j
(BR)DSS,Tj≤TJMAX
o
C
o
C
o
C
1/8
Page 2
STP60NS04Z
THERMAL DATA
R
thj-case
R
thj-case
R
thj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Valu e Unit
I
AR
E
Ther mal Res istance Junc t ion-case Max
Ther mal Res istance Junc t ion-case Ty p
Ther mal Res istance Junc t ion-ambie nt M a x
Ther mal Res istance Case -s ink Ty p
Maximum Lead Tempe rat ur e F or Soldering Pur p os e
l
Avalanche C urrent, R epetitive or Not-Repetitive
(pulse width limited by T
Single Pul se Avalanc he Ener gy
AS
(starting T
=25oC, ID=IAR,VDD=30V)
j
max, δ <1%)
j
1.07
0.85
62.5
0.5
300
60 A
400 mJ
o
C/W
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unless otherwisespecified)
(T
case
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
CLAMP
I
DSS
I
GSS
V
GSS
Drain-G ate Break dow n
Voltage
Zero Gate Voltage
Drain Curre nt (V
GS
=0)
Gat e- bod y Leakag e
Current (V
DS
=0)
Gate-Source
ID=1mA VGS=0
-40 < T
V
V
V
< 175oC
j
=16V Tj= 175oC50µA
DS
=± 10 V Tj=175oC
GS
= ± 16 V Tj=175oC
GS
33 V
50
150
IG= 100 µA18V
Break dow n Vo lt age
ON(∗)
Symbol Parameter Test Conditions Min. Typ. M ax. U nit
V
GS(th)
R
DS(on)
I
D(on)
Gate Threshold Voltage VDS=V
-40 < T
Sta t ic Drain-s our c e On
Resistance
VGS=10V ID=30A
=16V ID=30A
V
GS
On State Drain Current VDS>I
GSID
=1mA
< 150oC
j
D(on)xRDS(on)max
1.7 3 4.2 V
11
10
15
14
60 A
VGS=10V
DYNAMIC
µ
µA
mΩ
m
A
Ω
Symbol Parameter Test Conditions Min. Typ. M ax. U nit
g
(∗)Forward
fs
VDS>I
D(on)xRDS(on)maxID
=30 A 20 30 S
Tr ansc on duc tance
C
C
C
Input Capaci t ance
iss
Out put Capac itance
oss
Reverse Transfer
rss
VDS=25V f=1MHz VGS= 0 2500
800
150
3400
1100
200
Capacit a nc e
2/8
pF
pF
pF
Page 3
STP60NS04Z
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHINGON
Symbol Parameter Test Conditions Min. Typ. M ax. U nit
Q
Q
Q
Tot al Gate Charge
g
Gat e- Source Charge
gs
Gate-Drain Charge
gd
VDD=16V ID=60A VGS=10V 70
20
22
100 nC
SWITCHINGOFF
Symbol Parameter Test Conditions Min. Typ. M ax. U nit
t
r(Voff)
t
Off-voltage Rise Time
Fall T ime
t
f
Cross-over Time
c
V
R
=30V ID=60A
CLAM P
=4.7 ΩVGS=10V
G
(see test circuit, figure 5)
25
110
150
35
150
200
SOURCEDRAINDIODE
Symbol Parameter Test Conditions Min. Typ. M ax. U nit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed:Pulse duration= 300µs, duty cycle 1.5%
(•) Pulse width limited by safe operatingarea
Source-drain Current
(•)
Source-drain Current
60
240
(pulsed)
(∗)ForwardOnVoltage ISD=60A VGS=0 1.5 V
Reverse Recovery
rr
Time
Reverse Recovery
rr
ISD= 60 A di/dt = 100 A/µs
=25V Tj= 150oC
V
r
(see test circuit, figure 5)
65
0.15
Charge
Reverse Recovery
4.5
Current
nC
nC
ns
ns
ns
A
A
ns
µ
A
C
SafeOperating Area ThermalImpedance
3/8
Page 4
STP60NS04Z
OutputCharacteristics
Transconductance
TransferCharacteristics
Static Drain-sourceOn Resistance
Gate Charge vs Gate-sourceVoltage
4/8
CapacitanceVariations
Page 5
STP60NS04Z
NormalizedGate ThresholdVoltage vs
Temperature
ZeroGate VoltageDrain Current vs
Temperature
NormalizedOn Resistancevs Temperature
Source-drainDiode Forward Characteristics
5/8
Page 6
STP60NS04Z
Fig. 1:
UnclampedInductiveLoad Test Circuit
Fig. 3: SwitchingTimes Test Circuits For
ResistiveLoad
Fig. 2:
UnclampedInductive Waveform
Fig. 4: Gate Chargetest Circuit
Fig. 5:
Test CircuitFor InductiveLoad Switching
And Diode Recovery Times
6/8
Page 7
TO-220 MECHANICAL DATA
STP60NS04Z
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
mm inch
E
A
L4
D
F2
F1
G1
H2
G
F
P011C
C
D1
L2
Dia.
L5
L7
L6
L9
7/8
Page 8
STP60NS04Z
Information furnishedis believed tobeaccurateand reliable.However, STMicroelectronics assumes no responsibilityforthe consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publication are
subjecttochange without notice. This publication supersedes and replaces all information previouslysupplied. STMicroelectronicsproducts
are not authorized for use as critical components in lifesupport devicesor systemswithout express written approval of STMicroelectronics.
The STlogo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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8/8
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