Page 1
STP5NK100Z - STF5NK100Z
STW5NK100Z
N-CHANNEL 1000V - 2.7Ω - 3.5A TO-220/TO-220FP/TO-247
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
TYPE V
STF5NK100Z
STP5NK100Z
STW5NK100Z
■ TYPICAL R
■ EXTREMELY HIGH dv /d t CAPABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
DSSRDS(on)
1000 V
1000 V
1000 V
(on) = 2.7 Ω
DS
< 3.7 Ω
< 3.7 Ω
< 3.7 Ω
I
D
3.5 A (*)
3.5 A
3.5 A
Pw
30 W
125 W
125 W
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained thro ugh an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFET s including revolutionary MDmesh™ products.
Figure 1: Package
TO-220
TO-247
2
1
TO-220FP
3
Figure 2: Internal Schematic Diagram
3
2
1
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL F OR OFF-LINE POWER SUP PLIE S
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STF5NK100Z F5NK100Z TO-220FP TUBE
STP5NK100Z P5NK100Z TO-220 TUBE
STW5NK100Z W15NK100Z TO-247 TUBE
Rev. 3
1/13September 2005
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
STP5NK100Z
STW5NK100Z
V
I
V
V
DM
P
DS
DGR
GS
I
D
I
D
TOT
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
()
Drain Current (pulsed) 14 14 (*) A
Total Dissipation at TC = 25°C
3.5 3.5 (*) A
2.2 2.2 (*) A
125 30 W
Derating Factor 1 0.24 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
T
j
T
stg
() Pulse width limited by safe operat i ng area
≤3.5A, di/dt ≤200A/µs, VDD ≤ V
(1) I
SD
(*) Limited only by maximum temperature allowed
Insulation Withstand Voltage (DC) - 2500 V
Operating Junction Temperature
Storage Temperature
, Tj ≤ T
(BR)DSS
JMAX.
-55 to 150
-55 to 150
Table 4: Thermal Data
TO-220
TO-247
Rthj-case Thermal Resistance Junction-case Max 1 4.2 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
STF5NK100Z
1000 V
1000 V
TO-220FP
300 °C
°C
°C
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
3.5 A
250 mJ
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only t he device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to p r otect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STP5NK100Z - STF5NK100Z - ST W5NK100Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 0 1000 V
Voltage
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
= Max Rating
DS
V
= Max Rating,
DS
1
50
TC = 125°C
I
GSS
V
GS(th)
R
DS(on)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= ± 20 V ± 10 µA
GS
V
= VGS, ID = 100 µA 3
DS
3.75
4.5 V
VGS = 10 V, ID = 1.75 A 2.7 3.7 Ω
Resistance
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS = 15 V , ID = 1.75 A 4 S
fs
C
C
iss
C
oss
C
rss
oss eq
t
d(on)
t
r
t
d(off)
t
Q
Q
gs
Q
gd
f
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
= 25 V, f = 1 MHz,
V
DS
VGS = 0
1154
106
21.3
(3).Equivalent Outpu t Capacitance VGS = 0 V, VDS = 0 to 800 V 46.8 pF
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 500 V, ID = 1.75 A,
V
DD
R
= 4.7 Ω, V
G
GS
(see Figure 21)
= 800 V, ID = 3.5 A,
V
DD
V
= 10 V
GS
(see Figure 24)
= 10 V
22.5
7.7
51.5
19
42
7.3
21.7
59 nC
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse du rat i on = 300 µs, du ty cycle 1.5 % .
(2) Pulse width limited by safe operating area.
(3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 3.5 A, VGS = 0
= 3.5 A, di/dt = 100 A/µs
I
SD
V
= 35V
DD
(see Figure 22)
= 3.5 A, di/dt = 100 A/µs
I
SD
VDD = 35V, Tj = 150°C
(see Figure 22)
605
3.09
10.5
742
4.2
11.2
when VDS increase s from 0 to 80% V
oss
3.5
14
1.6 V
A
A
ns
µC
A
ns
µC
A
DSS
3/13
.
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 3: Safe Operating Area For TO-220
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance TO-220
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Safe Operating Area For TO-247
4/13
Figure 8: Thermal Impedance For TO-247
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STP5NK100Z - STF5NK100Z - ST W5NK100Z
Figure 9: Output Characteristics
Figure 10: Transconductance
Figure 12: Transfer Characteristics
Figure 13: Static Drain-Source On Resis tance
Figure 11: Gate Charge vs Gate-source Voltage
Figure 14: Capacitance Variations
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 15: Normalized Gate Threshold Voltage vs Tem pera tur e
Figure 16: S ource-Drain Forward Char acteristics
Figure 18: Normal ized On R esistance vs Temperature
Figure 19: Normalized BV
vs Temperature
DSS
Figure 17: Maximum Avalanche Energy vs Temperature
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STP5NK100Z - STF5NK100Z - ST W5NK100Z
Figure 20: Unclamped Inductive Load Test Circuit
Figure 21: Switching Times Test Circuit For Resistive Load
Figure 23: Unclamped Inductive Wafeform
Figure 24: Gate Charge Test Circuit
Figure 22: Test Circuit For Inductive Load Switching and Diode Recovery Times
7/13
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STP5NK100Z - STF5NK100Z - STW5NK100Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. T hese
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, i n compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
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STP5NK100Z - STF5NK100Z - ST W5NK100Z
TO-220FP MECHANICAL DATA
DIM.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
E
A
D
B
L3
L6
L7
F1
F
G1
H
F2
123
L4
L2
L5
G
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STP5NK100Z - STF5NK100Z - STW5NK100Z
TO-220 MECHANICAL DATA
DIM.
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.15 1.70 0.045 0.066
c 0.49 0.70 0.019 0.027
D 15.25 15.75 0.60 0.620
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.052
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
øP 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
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STP5NK100Z - STF5NK100Z - ST W5NK100Z
TO-247 MECHANICAL DATA
DIM.
A 4.85 5.15 0.19 0.20
A1 2.20 2.60 0.086 0.102
b 1.0 1.40 0.039 0.055
b1 2.0 2.40 0.079 0.094
b2 3.0 3.40 0.118 0.134
c 0.40 0.80 0.015 0.03
D 19.85 20.15 0.781 0.793
E 15.45 15.75 0.608 0.620
e5.45 0.214
L 14.20 14.80 0.560 0.582
L1 3.70 4.30 0.14 0.17
L2 18.50 0.728
øP 3.55 3.65 0.140 0.143
øR 4.50 5.50 0.177 0.216
S5.50 0.216
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Table 10: Revision History
Date Revision Description of Change s
27-Sep-2004 1 First release.
08-Oct-2004 2 Final datasheet
06-Sep-2005 3 Inserted Ecopack indication
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STP5NK100Z - STF5NK100Z - ST W5NK100Z
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is gra nted
by implic ati o n or ot h er wis e und er an y pat ent or pa te nt r igh ts of STMi cr oe l ect ro ni cs . Sp ec if i cat i on s ment i o ned i n th is p ub li c ati on ar e s ubj ec t
to change without not ice. This publication supersedes and replaces all information previously sup plied. STMicroelectr onics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2005 STMicroelectronics - All Rights Reserved
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