Datasheet stp5n120 Datasheet

Zener-protected SuperMESH™ Power MOSFET

Features

Typ e V

STP5N120 1200 V < 3.5 Ω 4.7 A 160 W

■ 100% avalanche tested

■ Extremely high dv/dt capability

■ ESD improved capability

■ New high voltage benchmark

■ Gate charge minimized

DSS

Application

■ Switching applications

R

DS(on)

I

D

STP5N120

N-channel 1200 V, 2.7 Ω, 4.7 A TO-220

P

W

3

2

1

TO-220

Description

The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage Power MOSFETs.

Table 1. Device summary

Order code Marking Package Packaging

STP5N120 5N120 TO-220 Tube

Figure 1. Internal schematic diagram

November 2009 Doc ID 13530 Rev 2 1/12

www.st.com

12

Contents STP5N120

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/12 Doc ID 13530 Rev 2

STP5N120 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

I

DM

V

DS

V

GS

I

D

I

D

Drain-source voltage (V

= 0) 1200 V

GS

Gate-source voltage ± 30 V

Drain current (continuous) at TC = 25 °C 4.7 A

Drain current (continuous) at TC = 100 °C 3 A

(1)

Drain current (pulsed) 18.8 A

Derating factor 1.28 W/°C

P

TOT

V

ESD(G-S)

dv/dt

T

T

stg

1. Pulse width limited by safe operating area

2. ISD ≤ 4.7 A, di/dt ≤ 200 A/µs, VDD ≤ 80% V

Total dissipation at TC = 25 °C 160 W

Gate source ESD (HBM-C = 100 pF,
R = 1.5 kΩ)

(2)

Peak diode recovery voltage slope 4 V/ns

Operating junction temperature

j

Storage temperature

(BR)DSS

4000 V

-55 to 150 °C

Table 3. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case max 0.78 °C/W

Rthj-amb

(1)

Thermal resistance junction-amb max 62.5 °C/W

T

1. When mounted on 1inch² FR-4 board, 2 oz Cu

Maximum lead temperature for soldering

l

purpose

300 °C

Table 4. Avalanche characteristics

Symbol Parameter Max value Unit

I

AS

E

AS

Avalanche current, repetitive or not­repetitive (pulse width limited by Tj max)

Single pulse avalanche energy
(starting TJ = 25 °C, ID=IAS, VDD= 50 V)

Doc ID 13530 Rev 2 3/12

4.7 A

400 mJ

Electrical characteristics STP5N120

2 Electrical characteristics

(T

= 25 °C unless otherwise specified)

CASE

Table 5. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

R

(BR)DSS

I

DSS

I

GSS

GS(th)

DS(on)

Drain-source breakdown
voltage

Zero gate voltage drain
current (VGS = 0)

Gate body leakage current

= 0)

(V

DS

Gate threshold voltage V

Static drain-source on
resistance

= 1 mA, VGS= 0 1200 V

I

D

= Max rating,

V

DS

= Max rating,Tc=125 °C

V

DS

V

= ± 20 V ±10 µA

GS

= VGS, ID = 100 µA 3 4 5 V

DS

V

= 10 V, ID= 2.3 A 2.7 3.5 Ω

GS

1

50µAµA

Table 6. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

(1)

C

oss eq.

g

fs

C

C

C

Forward transconductance V

Input capacitance

iss

Output capacitance 139 pF

oss

Reverse transfer

rss

capacitance

Equivalent output

(2)

capacitance

= 15 V, ID = 2.3 A 5.8 S

DS

2004

V

=25 V, f=1 MHz, VGS=0 -

DS

19 pF

V

= 0, VDS = 0 to 960 V - 89 - pF

GS

-

pF

R

Q

Q

Q

1. Pulsed: pulse duration=300µs, duty cycle 1.5%

2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% V

Intrinsic gate resistance f = 1MHz open drain - 2.2 - Ω

G

Total gate charge

g

Gate-source charge

gs

Gate-drain charge

gd

DSS

V

= 960 V, ID = 4.7 A

DD

=10 V

V

GS

(see Figure 15)

Table 7. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

4/12 Doc ID 13530 Rev 2

Turn-on delay time

t

Rise time

r

Turn-off delay time

t

Fall time

f

= 600 V, ID = 2.3 A,

V

DD

=4.7 Ω, VGS=10 V

R

G

(see Figure 17)

57

-

10
31

18

9

­42

30

nC

-

nC
nC

ns
ns

­ns

ns

STP5N120 Electrical characteristics

Table 8. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

SD

I

SDM

V

SD

t

Q

I

RRM

t

Q

I

RRM

1. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Source-drain current
Source-drain current (pulsed)

(1)

Forward on voltage ISD= 4.7 A, VGS=0 - 1.6 V

Reverse recovery time

rr

Reverse recovery charge

rr

Reverse recovery current

Reverse recovery time

rr

Reverse recovery charge

rr

Reverse recovery current

= 4.7 A, VDD= 60 V

I

SD

di/dt = 100 A/µs,

(see Figure 16)

ISD= 4.7 A,VDD= 60 V
di/dt=100 A/µs,

Tj=150 °C(see

Figure 16)

-

760

-

5

14

880

-

7

160

4.7

18.8mAA

ns
µC

A

ns
µC

A

Table 9. Gate-source Zener diode

Symbol Parameter Test conditions Min Typ. Max Unit

BV

Gate-source breakdown voltage Igs ± 1mA, (open drain) 30 V

GSO

The built-in-back Zener diodes have specifically been designed to enhance not only the
device’s ESD capability, but also to make them safely absorb possible voltage transients that
may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.

Doc ID 13530 Rev 2 5/12

Electrical characteristics STP5N120

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance

I

D

(A)

10

Limited by max R

DS(on)

Tj=150°C
Tc=25°C

1

Operation in this area is

0.1

Sinlge
pulse

0.01
10

0.1

Figure 4. Output characteristics Figure 5. Transfer characteristics

1

100

1000

ID

(A)

8

VGS=10V

7

6

5

4

3

2

1

0

0

10

20

AM03232v1

10µs
100µs

1ms

10ms

DS

V

V

DS(V)

(V)

AM03233v1

6V

5V

ID

(A)

10

AM03234v1

VDS=25V

8

6

4

2

0

2

0

4

8

6

10

V

GS(V)

Figure 6. Normalized B

BV

DSS

vs temperature Figure 7. Static drain-source on resistance

VDSS

AM03241v1

RDS(on)

(norm)

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-100

-50

0

50

100

150

T

J

(°C)

6/12 Doc ID 13530 Rev 2

(Ω)

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

1.0

ID=2.3A

GS=10V

V

2.0

3.0

4.0

AM03235v1

I

D(A)

STP5N120 Electrical characteristics

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations

VGS

(V)

12

10

DS

V

VDD=480V

D=4.7A

I

8

6

4

2

VGS

AM03236v1

1000

800

600

400

200

C

(pF)

1000

100

10

AM03237v1

Ciss

Coss

Crss

0

0

10

20

30

40

50

60

Q

0

g(nC)

Figure 10. Normalized gate threshold voltage

VGS(th)
(norm)

vs temperature

1.20

1.00

0.80

0.60

0.40

-100

-50

AM03238v1

T

50

0

100

150

J(°C)

Figure 12. Source-drain diode forward

characteristics

V

SD

(V)

0.9

0.8

0.7

0.6

0.5

0.4
0

1

TJ=-50°C

2

3

TJ=25°C

4

T

5

J

=150°C

6

AM03240v1

I

SD

(A)

1

0.1

1

10

100

1000

V

DS(V)

Figure 11. Normalized on resistance vs

temperature

150

AM03239v1

T

J

R

DS(on)

(norm)

2.5

2.0

1.5

1.0

0.5

0

-100

-50

50

0

100

Figure 13. Maximum avalanche energy vs

temperature

120

AM03242v1

140

EAS

(mJ)

400

350

300

250

200

150

100

50

ID=4.7 A

V

DD=50 V

0

0

20

40

60

80

100

(°C)

T

J(°C)

Doc ID 13530 Rev 2 7/12

Test circuits STP5N120

3 Test circuits

Figure 14. Switching times test circuit for

resistive load

Figure 16. Test circuit for inductive load

switching and diode recovery times

Figure 15. Gate charge test circuit

Figure 17. Unclamped inductive load test

circuit

Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform

8/12 Doc ID 13530 Rev 2

STP5N120 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Doc ID 13530 Rev 2 9/12

Package mechanical data STP5N120

TO-220 type A mechanical data

Dim

Min Typ Max

mm

A 4.40 4.60

b 0.61 0.88

b1 1.14 1.70

c0.48 0.70
D 15.25 15.75

D1 1.27

E10 10.40
e 2.40 2.70

e1 4.95 5.15

F1.23 1.32
H1 6.20 6.60
J1 2.40 2.72

L13 14
L1 3.50 3.93

L20 16.40
L3028.90
∅P 3.75 3.85

Q 2.65 2.95

10/12 Doc ID 13530 Rev 2

0015988_Rev_S

STP5N120 Revision history

5 Revision history

Table 10. Revision history

Date Revision Changes

21-May-2007 1 First release

02-Nov-2009 2

Document status promoted from preliminary data to datasheet.
Updated mechanical data.

Doc ID 13530 Rev 2 11/12

STP5N120

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12/12 Doc ID 13530 Rev 2