Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
R
DS(on)
3.3 Ω
3.3 Ω
I
4 A
4 A
D
STP4NB80FP
PowerMESH MOSFET
3
2
1
TO-220 TO-220FP
INTERNAL SCHEMAT I C DIAGRAM
3
2
1
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED S WITCHI NG
■ SWITCH MODE PO W E R S UPPLIES (SM PS )
■ DC-AC CONVERT E RS F OR W ELDI NG
EQUIPMENT AND UN INTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MA XIMU M RAT INGS
SymbolParameterValueUnit
STP4NB80STP4NB80FP
V
V
V
I
DM
P
dv/dt(1) Peak Diode Recovery voltage slope4.54.5V/ns
V
T
(•) Pulse width limited by safe operating area (1) ISD ≤4 A, di/dt ≤ 200 A/µs, VDD ≤ V
(*) Limited only by maximum temperature allowed
September 2001
Drain-source Voltage (VGS = 0)800V
DS
Drain- gate Voltage (RGS = 20 kΩ)
DGR
Gate-source Voltage± 30V
GS
I
Drain Current (continuous) at Tc = 25 oC44(*)A
D
Drain Current (continuous) at Tc = 100 oC2.42.4(*)A
I
D
800V
(•)Drain Current (pulsed)1616A
Total Dissipation at Tc = 25 oC10035W
tot
Derating Factor0.80.28W/
Insulation Withstand Voltage (DC)2500V
ISO
Storage Temperature-65 to 150
stg
Max. Operating Junction Temperature150
T
j
, Tj ≤ T
(BR)DSS
JMAX
o
C
o
C
o
C
1/9
Page 2
STP4NB80/FP
THERMAL DATA
TO-220TO220-FP
R
thj-case
R
thj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTI CS
SymbolParameterMax ValueUnit
I
AR
E
Thermal Resistance Junction-case Max1.253.6
Thermal Resistance Junction-ambient Max
Thermal Resistance Case-sink Typ
Maximum Lead Temperature For Soldering Purpose
l
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
Single Pulse Avalanche Energy
AS
(starting T
= 25 oC, ID = IAR, V
j
max)
j
DD
= 50 V)
62.5
0.5
300
4A
230mJ
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS (T
= 25 oC unless otherwise specif ied)
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source
I
= 250 µA V
D
GS
= 0
800V
Breakdown Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
= Max Rating
V
DS
V
= Max Rating Tc = 125 oC
DS
V
= ± 30 V
GS
1
50
± 100nA
ON (∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS ID = 250 µA
V
DS
VGS = 10V ID = 2 A33.3Ω
345V
Resistance
I
D(on)
On State Drain Current VDS > I
V
= 10 V
GS
D(on)
x R
DS(on)max
4A
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(∗)Forward
fs
Transconductance
C
C
C
Input Capacitance
iss
Output Capacitance
oss
Reverse Transfer
rss
Capacitance
VDS > I
V
DS
x R
D(on)
DS(on)max
= 25 V f = 1 MHz V
ID = 2 A1.52.9S
= 0700
GS
95
920
126
9
12
µA
µA
pF
pF
pF
2/9
Page 3
STP4NB80/F P
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
t
Turn-on delay Time
Rise Time
r
V
= 400 V ID = 2 A
DD
RG = 4.7 Ω VGS = 10 V
14
20
8
12
ns
ns
Q
Q
Q
Total Gate Charge
g
Gate-Source Charge
gs
Gate-Drain Charge
gd
V
= 640 V ID = 4 A V
DD
= 10 V21
GS
7
9
29nC
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
r(Voff)
t
t
Off-voltage Rise Time
Fall Time
f
Cross-over Time
c
V
= 640V ID = 4 A
DD
= 4.7 Ω VGS = 10 V
R
G
12
9
16
17
13
22
SOURCE DRAIN DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
4
16
I
SDM
I
SD
Source-drain Current
(•)
Source-drain Current
(pulsed)
V
(∗)Forward On VoltageISD =4 A VGS = 01.6V
SD
t
Q
Reverse Recovery
rr
Time
Reverse Recovery
rr
I
= 4 A di/dt = 100 A/µs
SD
V
= 100 V Tj = 150 oC
DD
600
3.3
Charge
I
RRM
Reverse Recovery
11
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
nC
nC
ns
ns
ns
A
A
ns
µC
A
Safe Operating A rea for TO- 220Safe Operating Ar ea for TO-220FP
3/9
Page 4
STP4NB80/FP
Thermal Impedance for TO- 220
Output Charact eris t ics
Thermal Impedance forTO-220FP
Transfer Charact eris t ics
Transconductanc e
4/9
Static Drain-source O n Resis tance
Page 5
STP4NB80/F P
Gate Charge vs Gate- source Volt ag e
Normalized Gate Thr eshold Volt age vs
Temperature
Capacitance Variations
Normalized On Resistance vs Temper atur e
Source-drain Diode Forward Charact er ist ics
5/9
Page 6
STP4NB80/FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switc hing Times Tes t Cir cuit s Fo r
Resistive Load
Fig. 2: Unclamped Inductive W av efor m
Fig. 4: Gate Charge tes t Cir cuit
Fig. 5: Test Circuit For Inductiv e Load Sw itching
And Diode Recovery Times
6/9
Page 7
TO-220 MECHANICAL DATA
STP4NB80/FP
DIM.
A 4.404.600.173 0.181
C1.231.320.048 0.052
D2.402.720.094 0.107
E 0.490.700.019 0.027
F 0.610.880.024 0.034
F11.141.700.044 0.067
F21.141.700.044 0.067
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such inform ation nor for any infringe ment o f patents or other rig hts o f third par ties which ma y resul t from i ts use. N o li cen se is
granted by implicatio n or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical compo nents in life support devices or systems without express written approval of STMicroelectronics.