Page 1
STP4NB100
N - CHANNEL1000V - 4Ω - 3.8A - TO-220/TO-220FP
TYPE V
STP4NB100
STP4NB100FP
■ TYPICALR
■ EXTREMELYHIGHdv/dt CAPABILITY
■ 100%AVALANCHETESTED
■ VERYLOW INTRINSIC CAPACITANCES
■ GATECHARGE MINIMIZED
DS(on)
DSS
1000 V
1000 V
=4
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
Ω
R
DS(on)
<4.4Ω
<4.4
Ω
I
D
3.8 A
3.8 A
STP4NB100FP
PowerMESH MOSFET
3
2
1
TO-220 TO-220FP
INTERNAL SCHEMATIC DIAGRAM
3
2
1
APPLICATIONS
■ HIGHCURRENT, HIGH SPEEDSWITCHING
■ SWITCHMODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENTANDUNINTERRUPTIBLE
POWERSUPPLIESAND MOTORDRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
STP 4NB100 ST P4NB100F P
V
V
V
I
DM
P
dv/dt(
V
T
(•) Pulse width limited by safeoperating area (1)ISD≤ 3.8A, di/dt ≤ 200 A/µs, VDD≤ V
(*) Limited only by maximum temperatureallowed
October 1999
Drain-source V oltage (VGS=0) 1000 V
DS
Drain- gate Voltag e (RGS=20kΩ)
DGR
Gate-source Voltage ± 30 V
GS
Drain Current ( co nt inu ous) at Tc=25oC 3.8 3.8(* ) A
I
D
Drain Current ( co nt inu ous) at Tc= 100oC 2.4 2.4(* ) A
I
D
1000 V
(•) Drain Current (pulsed) 15.2 15.2 A
Tota l Dissipati on at Tc=25oC 125 40 W
tot
Derating F actor 1 0 .32 W/
1) Peak Diode Recove r y vo lt age slope 4 4 V/ns
Insulation Withstand Voltage (DC) 2000 V
ISO
Stor age Temper ature -65 t o 150
stg
Max. Op er at i ng Ju nc tion Temperature 150
T
j
(BR)DSS
,Tj≤T
JMAX
o
C
o
C
o
C
1/9
Page 2
STP4NB100/STP4NB100FP
THERMAL DATA
TO-220 TO- 220F P
R
thj-case
R
thj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
Ther mal Resistanc e Junct ion-case Ma x 1 3.12
Ther mal Resistanc e Junct ion-ambient Max
Ther mal Resistanc e Case-sink Typ
Maximum Lead Te m pe ra t ure For So lder ing Purp ose
l
Avalanche C urrent, R epetitive or Not-Repetitive
(pulse width limited by T
Single P ul s e Avalan che Energy
AS
(starting T
=25oC, ID=IAR,VDD=50V)
j
max)
j
62.5
0.5
300
3.8 A
360 mJ
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unless otherwisespecified)
(T
case
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
=250µAVGS=0
I
D
1000 V
Break dow n Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Cur rent (V
GS
Gat e- bod y L eak ag e
Current (V
DS
=0)
=0)
V
=MaxRating
DS
=MaxRating Tc=125oC
V
DS
=± 30 V
V
GS
1
50
± 100 nA
ON(∗)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Sta t ic Drain -s ource On
V
DS=VGSID
= 250µA
VGS=10V ID=2A 4 4.4 Ω
345V
Resistance
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on)max
3.8 A
VGS=10V
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(∗)Forward
fs
Tr ansc on duc tance
C
C
C
Input Capac i t ance
iss
Out put Capacitanc e
oss
Reverse Tr ansfer
rss
Capacit a nc e
VDS>I
D(on)xRDS(on)maxID
=2A 1.5 3 S
VDS=25V f=1MHz VGS= 0 1400
117
7
µ
µA
pF
pF
pF
A
2/9
Page 3
STP4NB100/STP4NB100FP
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHINGON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Turn-on Time
r
Rise Ti m e
t
VDD=500V ID=2A
R
=4.7
G
Ω
VGS=10V
20
9
(see test circuit, figure 3)
Q
Q
Q
Tot al Gat e Charge
g
Gat e- Source Charge
gs
Gate-Drain Charge
gd
VDD= 800 V ID=4A VGS=10V 32
12
11
45 nC
SWITCHINGOFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
t
Off-voltage Rise Tim e
Fall T ime
f
Cross-over T ime
c
VDD=800V ID=4A
=4.7 ΩVGS=10V
R
G
(see test circuit, figure 5)
15
12
20
SOURCEDRAINDIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operatingarea
Source-drain Current
(•)
Source-drain Current
3.8
15.2
(pulsed)
(∗)ForwardOnVoltage ISD=3.8A VGS=0 1.6 V
Reverse Recovery
rr
Time
Reverse Recovery
rr
=4A di/dt=100A/µs
I
SD
= 100 V Tj=150oC
V
DD
(see test circuit, figure 5)
750
5.4
Charge
Reverse Recovery
14.5
Current
ns
ns
nC
nC
ns
ns
ns
A
A
ns
µ
A
C
SafeOperating Area for TO-220 SafeOperating Area for TO-220FP
3/9
Page 4
STP4NB100/STP4NB100FP
ThermalImpedancefor TO-220
OutputCharacteristics
ThermalImpedanceforTO-220FP
TransferCharacteristics
Transconductance
4/9
Static Drain-sourceOn Resistance
Page 5
STP4NB100/STP4NB100FP
Gate Charge vs Gate-sourceVoltage
NormalizedGate ThresholdVoltage vs
Temperature
CapacitanceVariations
NormalizedOn Resistance vs Temperature
Source-drainDiode Forward Characteristics
5/9
Page 6
STP4NB100/STP4NB100FP
Fig. 1:
UnclampedInductiveLoad Test Circuit
Fig. 3: SwitchingTimes Test Circuits For
ResistiveLoad
Fig. 2:
UnclampedInductive Waveform
Fig. 4: Gate Chargetest Circuit
Fig. 5:
Test Circuit For InductiveLoad Switching
And Diode Recovery Times
6/9
Page 7
TO-220 MECHANICAL DATA
STP4NB100/STP4NB100FP
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
mm inch
E
A
L4
D
F2
F1
G1
H2
G
F
P011C
C
D1
L2
Dia.
L5
L7
L6
L9
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Page 8
STP4NB100/STP4NB100FP
TO-220FP MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 0.385 0.417
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
mm inch
E
A
D
B
L3
L6
L7
¯
F1
F
G1
H
G
F2
123
L2
L4
8/9
Page 9
STP4NB100/STP4NB100FP
Information furnishedis believed tobeaccurateand reliable.However, STMicroelectronics assumesno responsibilityfor the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publicationare
subjecttochange without notice. This publicationsupersedesandreplaces all information previouslysupplied. STMicroelectronicsproducts
are not authorized for use as critical components in life support devicesor systemswithout express written approval of STMicroelectronics.
The STlogo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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