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1/8April 2001
STP40NF10L
N-CHANNEL 100V - 0.028Ω - 40A TO-2 20
LOW GATE CHARGE STripFET™ POWER MOSFET
(1) Starting Tj = 25°C, ID = 20A, VDD = 40V
■ TYPICAL R
DS
(on) = 0.028Ω
■ EXCEPTIONA L dv/d t CAPABILITY
■ 100% AVALANCHE TESTED
■ APPLICATION ORIENTED
CHARACTERIZATION
DESCRIPTION
This Power Mosfet series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated D C-DC
converters for T el ecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.
APPLICATIONS
■ HIGH-EFFICIENCY DC-DC CONVERTERS
■ UPS AND MOTOR CONTROL
■ AUTOMOTIVE
ABSOLUTE MAXIMUM RATINGS
(●) Pulse width limited by safe operating area
TYPE V
DSS
R
DS(on)
I
D
STP40NF10L 100 V < 0.033
Ω
40 A
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0)
100 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
100 V
V
GS
Gate- source Voltage ± 15 V
I
D
Drain Current (continuos) at TC = 25°C
40 A
I
D
Drain Current (continuos) at TC = 100°C
25 A
I
DM
(●)
Drain Current (pulsed) 160 A
P
TOT
Total Dissipation at TC = 25°C
150 W
Derating Factor 1 W/°C
E
AS
(1)
Single Pulse Avalanche Energy 430 mJ
T
stg
Storage Temperature –65 to 175 °C
T
j
Max. Operating Junction Temperature 175 °C
TO-220
1
2
3
INTERNAL SCHEMATIC DIAGRAM
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STP40NF10L
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THERMA L D ATA
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(1)
DYNAMIC
Rthj-case Thermal Resistance Junction-case Max 1 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose 300 °C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0 100 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1µA
V
DS
= Max Rating, TC = 125 °C
10 µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ± 15V ±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= VGS, ID = 250µA
1 1.7 2.5 V
R
DS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 20 A
0.028 0.033
Ω
VGS = 5V, ID = 20 A
0.030 0.036
Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1) Forward Transconductance VDS = 15V, ID= 20 A 25 S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, VGS = 0
2300 pF
C
oss
Output Capacitance 290 pF
C
rss
Reverse Transfer
Capacitance
125 pF
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STP40NF10L
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cyc l e 1.5 %.
2. Pulse width li mited by safe operating ar ea.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Turn-on Delay Time
V
DD
= 50 V, ID = 20 A
R
G
= 4.7Ω VGS = 4.5V
(see test circuit, Figure 3)
25 ns
t
r
Rise Time 82 ns
Q
g
Total Gate Charge VDD = 80V, ID =40A,VGS = 5V 46
64
nC
Q
gs
Gate-Source Charge 12 nC
Q
gd
Gate-Drain Charge 22 nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off-Delay Time
Fall Time
VDD = 50 V, ID = 20 A,
RG=4.7Ω, V
GS
= 4.5V
(see test circuit, Figure 3)
64
24
ns
ns
t
d(off)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
Vclamp =80V, I
D
= 40 A
RG=4.7Ω, V
GS
= 4.5V
(see test circuit, Figure 3)
51
29
53
ns
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
Source-drain Current 40 A
I
SDM
(1)
Source-drain Current (pulsed) 160 A
VSD (2)
Forward On Voltage
ISD = 40 A, VGS = 0
1.3 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 40 A, di/dt = 100A/µs,
VDD = 30V, Tj = 150°C
(see test circuit, Figure 5)
110
467
8
ns
nC
A
Safe Operating Area Thermal Impeda nce
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STP40NF10L
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Transfer Characteristics
Gate Charge vs Gate-source Voltage
Static Drain-source On ResistanceTransco nductance
Output Characteristics
Capacitance Variations
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5/8
STP40NF10L
Normalized Gate Threshold Volta ge vs
Temperature
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
Normalized Drain-Source Breakdown vs
Temperature
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
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7/8
STP40NF10L
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
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STP40NF10L
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any pa tent or patent rights of STM icroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical compo nents in life support devices or systems without express written approval of STMicroelectronics.
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