Page 1
N - CHANNEL 100V - 0.030Ω - 40A TO-220
LOW GATE CHARGE STripFET POWER MOSFET
TYPE V
DSS
ST P40NF10 100 V < 0.0 35 Ω 40 A
■ TYPICALR
■ EXCEPTIONALdv/dtCAPABILITY
■ 100%AVALANCHETESTED
■ APPLICATIONORIENTED
DS(on)
= 0.030 Ω
CHARACTERIZATION
R
DS(on)
I
STP40NF10
PRELIMINARY DATA
D
DESCRIPTION
This MOSFET series realized with STMicroelec-
3
2
1
tronics unique STripFET process has specifically
been designed to minimize input capacitanceand
TO-220
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency, high-frequency isolated DC-DC converters for Telecom and
Computerapplications. It is also intended for any
applicationswith low gate drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH-EFFICIENCYDC-DC CONVERTERS
■ UPSAND MOTORCONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Uni t
V
V
V
I
DM
P
E
AS
T
(•) Pulse width limitedby safe operating area (1) starting Tj
Dra in- sour c e Volta ge (VGS= 0) 100 V
DS
Drain- gate Voltage (RGS=20kΩ) 100 V
DGR
Gate-s ource Voltage ± 20 V
GS
Dra in Cu rr ent (cont i nuous) at Tc=25oC40A
I
D
Dra in Cu rr ent (cont i nuous) at Tc= 100oC25A
I
D
(
Dra in Cu rr ent (pulsed) 160 A
•)
Tot al Dissipatio n at Tc=25oC 140 W
tot
Der ati ng F a c tor 0.93 W/
(1) Single Pu ls e Avalanche Energy 135 mJ
St orage T e m pe ra t ure -65 to 175
stg
Max. Operating Jun ct ion Te mperature 175
T
j
=25oC,ID=40A , VDD= 50V
o
C
o
C
o
C
May 2000
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STP40NF10
THERMAL DATA
R
thj-case
R
thj-amb
T
Ther mal Resistanc e Junct ion-case Max
Ther mal Resistanc e Junct ion-ambient Max
Maximum Lead Tempe ra tur e For Soldering Purpos e
l
1.07
62.5
300
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unless otherwisespecified)
(T
case
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID=250µAVGS= 0 100 V
Break dow n Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gat e- bod y Leak ag e
Current (V
DS
=0)
=0)
V
=MaxRating
DS
=MaxRating Tc=125oC
V
DS
V
= ± 20 V ± 100 nA
GS
1
10
ON(∗)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage VDS=VGSID= 250 µA22.84V
Sta t ic Drain-s ource On
VGS=10V ID= 20 A 0.030 0.035 Ω
Resistance
I
D(on)
On State Drain Current VDS>I
D(on)xRDS(on)max
40 A
VGS=10V
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(∗)Forward
fs
Tr ansc on duc tance
C
C
C
Input Capaci t anc e
iss
Out put Capac it ance
oss
Reverse Transfer
rss
Capacit a nc e
VDS>I
D(on)xRDS(on)maxID
=20 A 20 S
VDS=25V f=1MHz VGS= 0 1800
270
110
µA
µ
pF
pF
pF
A
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STP40NF10
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHINGON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Tur n-on Delay T ime
Rise Tim e
t
r
VDD=50V ID=20A
R
=4.7
G
Ω
VGS=10V
28
63
(Resis t iv e Load, s ee fig. 3 )
Q
Q
Q
Tot al Gate Charge
g
Gat e- Source Charge
gs
Gate-Drain Charge
gd
VDD=80V ID=40A VGS=10V 60
10
23
80 nC
SWITCHINGOFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
Tur n-of f Dela y T im e
t
Fall T ime
f
VDD=50V ID=20A
=4.7 Ω VGS=10V
R
G
84
28
(Resis t iv e Load, s ee fig. 3 )
t
d(off)
Off-voltage Ris e T ime
t
Fall T ime
f
t
Cross-over Time
c
Vclamp = 80 V ID=40A
=4.7 Ω VGS=10V
R
G
(Indu ct iv e Load , see fig. 5)
71
36
70
SOURCEDRAINDIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operatingarea
Source-drain Current
(•)
Source-drain Current
40
160
(pulsed)
(∗)ForwardOnVoltage ISD=40A VGS=0 1.5 V
Reverse Recovery
rr
Time
Reverse Recovery
rr
ISD= 40 A di/dt = 100 A/µs
=50V Tj=150oC
V
DD
(see test circuit, fig. 5)
114
456
Charge
Reverse Recovery
8
Current
ns
ns
nC
nC
ns
ns
ns
ns
ns
A
A
ns
nC
A
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STP40NF10
Fig. 1
: UnclampedInductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
ResistiveLoad
Fig. 2
: UnclampedInductiveWaveform
Fig. 4: Gate Charge test Circuit
Fig. 5
: Test Circuit For Inductive Load Switching
And Diode Recovery Times
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Page 5
TO-220 MECHANICAL DATA
STP40NF10
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
mm inch
E
A
L4
D
F2
F1
G1
H2
G
F
P011C
C
D1
L2
Dia.
L5
L7
L6
L9
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STP40NF10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademarkof STMicroelectronics
2000 STMicroelectronics – Printed in Italy – All Rights Reserved
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