Page 1
STP3NC50
N-CHANNEL 500V - 3Ω - 2.8A T O-220
PowerMesh™II MOSFET
TYPE V
DSS
STP3NC50 500 V < 4
■ TYPICAL R
■ EXTREMELY HIGH dv /d t C APABILITY
■ 100% AVALANCHE TESTED
■ NEW HIGH VOLTAGE BENCHMARK
■ GATE CHARGE MINIMIZED
(on) = 3 Ω
DS
R
DS(on)
I
D
Ω
2.8 A
DESCRIPTION
The PowerMESH
generation of MESH OVERLAY
™II is the evolution of the first
™. The layout re-
finements introduced greatly improve the Ron*area
figure of merit while keeping the device at the lea ding edge for what concerns swithing speed, gate
charge and ruggedness.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLI ES ( SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVER
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
(1)
j
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
500 V
500 V
Gate- source Voltage ±30 V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
2.8 A
1.8 A
Drain Current (pulsed) 11.2 A
Total Dissipation at TC = 25°C
75 W
Derating Factor 0.6 W/°C
Storage Temperature –60 to 150 °C
Max. Operating Junction Temperature 150 °C
(1)ISD ≤ 2.8A, di/dt ≤100A/µs, VDD ≤ V
(BR)DSS
, Tj ≤ T
JMAX
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt Peak Diode Recovery voltage slope 3 V/ns
T
stg
T
(•)Pu l se width limited by safe operati ng area
.
1/8May 2001
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STP3NC50
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 1.67 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
l
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
2.8 A
110 mJ
ID = 250 µA, VGS = 0 500
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±30V ±100 nA
GS
1µA
50 µA
V
ON
(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
V
= VGS, ID = 250µA
DS
VGS = 10V, ID = 1.4 A
234V
34
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 45 pF
Reverse Transfer
Capacitance
I
D
V
= 1.4A
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
2S
260 pF
5pF
Ω
2/8
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STP3NC50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Turn-on Delay Time
t
r
Rise Time
= 250V, ID = 1.4 A
V
DD
RG= 4.7Ω VGS = 10V
(see test circuit, Figure 3)
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 400V, ID = 2.8 A,
V
DD
VGS = 10V
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 400V, ID = 2.8 A,
t
r(Voff)
t
t
Off-voltage Rise Time
f
c
Fall Time
Cross-over Time
V
DD
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 %.
2. Pulse width li mited by safe operating area .
Source-drain Current 2.8 A
(2)
Source-drain Current (pulsed) 11.2 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge 2200 nC
ISD = 2.8 A, VGS = 0
I
= 2.8A, di/dt = 100A/µs,
SD
V
= 100V, Tj = 150°C
DD
(see test circuit, Figure 5)
Reverse Recovery Current 11.5 A
10
10
10
13.5 nC
2.5
4.5
10
8
20
1.6 V
380 ns
ns
ns
nC
nC
ns
ns
ns
Safe Operating Area Thermal Impedence
3/8
Page 4
STP3NC50
Output Characteristics
Transfer Characteristics
Static Drain-source On ResistanceTransconductance
Gate Charge vs Gate-source Voltage
4/8
Capacitance Variations
Page 5
STP3NC50
Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forw ard Ch aracteristi cs
Normalized On Resistance vs Temperatur e
5/8
Page 6
STP3NC50
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
Page 7
E
TO-220 MECHANICAL DATA
STP3NC50
DIM.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A
C
D
L5
Dia.
L7
D1
L6
L2
L9
F1
G1
F
H2
G
F2
L4
P011C
7/8
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STP3NC50
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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