The STM7E1 consists in 7 identical ISDN E1
channels, each channel corresponding to 4 main
low-resistant switches (a and b) and 2 auxiliary
switches (c and d). The switches posi tion s in all
the channels are identical and c ontrolled by a
unique control resource driven by the digital inputs
Lm, Ls and Sc.
In each c hannel, t he TX and RX lines can be
switched bet ween a Main port or a Spare-port by
the main switches: if both "a" switches are closed
and both "b" switches are open, the Main port is
connected to the line, while if both "a" switches
are open and both "b' switches are clo se d, the
spare port is connected to the line.
The 2 auxiliary switches enable to close a local
loop between the TX and RX a ccess of a port: if
"c" is closed, the Spare port RX and TX access is
connected between each other to fo rm a local
loop, while if "d" is closed, the Main port RX and
TX access is connected between each other to
form a local loop.
TQFP64
The Spare port is only used for test purpose on the
system board while the Main port is the
communicationchannel.Consequently,a
switching from the Main port to the Spare port
occurs very rarely (<10 times a day).
The power sup plies of the chip need to be de
coupled properly. This means that at least one
external capacitor C1 must be connected in
between GND and VPOS, one external c apac it or
C2 between GND and VNE G, and one external
capacitor C3 between each pair of VNEG and
VPOS.
ORDERING CODES
Type
STM7E1A-40 to 85 °CTQFP64 (Tray)160 parts per Tray
STM7E1AR-40 to 85 °CTQFP64 (Tape & Reel)1000 parts per reel
Temperature
Range
PackageComments
1/10December 2002
Page 2
STM7E1A
PIN CONFIGURATION
PIN DESCRIPTION
PlN N°SYMBOLTYPENAME AND FUNCTION
1, 17, 33, 47V
2Txm#2IOAChannel 2: TX main port
3Tx#2IOAChannel 2: TX line
4Txs#2IOAChannel 2: TX spare port
5, 12, 21, 25, 29,
38, 52, 56, 60
6Rxm#3IOAChannel 3: RX main port
7Rx#3IOAChannel 3: RX line
8Rxs#3IOAChannel 3: RX spare port
9Txm#3IOAChannel 3: TX main port
10Tx#3IOAChannel 3: TX line
11Txs#3IOAChannel 3: TX spare port
13Rxm#4IOAChannel 4: RX main port
14Rx#4IOAChannel 4: RX line
15Rxs#4IOAChannel 4: RX spare port
16, 34, 48, 64
18Txm#4IOAChannel 4: TX main port
19Tx#4IOAChannel 4: TX line
20Txs#4IOAChannel 4: TX spare port
22Rxm#5IOAChannel 5: RX main port
23Rx#5IOAChannel 5: RX line
24Rxs#5IOAChannel 5: RX spare port
26Txm#5IOAChannel 5: TX main port
27Tx#5IOAChannel 5: TX line
28Txs#5IOAChannel 5: TX spare port
30Rxm#6IOAChannel 6: RX main port
(1)
NEG
GNDG
V
(2)
POS
P
P
Negative Power Supply
Voltage Reference for digital inputs
Positive Power Supply
2/10
Page 3
PlN N°SYMBOLTYPENAME AND FUNCTION
31Rx#6IOAChannel 6: RX line
32Rxs#6IOAChannel 6: RX spare port
35ScIControl digital input
36LsIControl digital input
37LmIControl digital input
39Txm#6IOAChannel 6: TX main port
40Tx#6IOAChannel 6: TX line
41Txs#6IOAChannel 6: TX spare port
42ModeIControl Digital Input
43Rxm#0IOAChannel 0: RX main port
44Rx#0IOAChannel 0: RX line
45Rxs#0IOAChannel 0: RX spare port
46TEST/SnIChannel 6: RX main port
49Txm#0IOAChannel 0: TX main port
50Tx#0IOAChannel 0: TX line
51Txs#0IOAChannel 0: TX spare port
53Rxm#1IOAChannel 1: RX main port
54Rx#1IOAChannel 1: RX line
55Rxs#1IOAChannel 1: RX spare port
57Txm#1IOAChannel 1: TX main port
58Tx#1IOAChannel 1: TX line
59Txs#1IOAChannel 1: TX spare port
61Rxm#2IOAChannel 2: RX main port
62Rx#2IOAChannel 2: RX line
63Rxs#2IOAChannel 2: RX spare port
NOTE 1: All VNEG pins to be connected together on board.
NOTE 2: All VPOS pins to be connected together on board.
STM7E1A
3/10
Page 4
STM7E1A
TYPICAL OPERATING CIRCUIT
Tx#0
Rx#0
LmLsScMODETEST/Sn
Control Decoding
Level Shifting & Buffering
CHANNEL 0
a
b
cd
a
b
Txm#0
Txs#0
Rxm#0
Rxs#0
Tx#1
Rx#1
Tx#6
Rx#6
CHANNEL 1
CHANNEL 6
VNEGGND
Txm#1
Txs#1
Rxm#1
Rxs#1
Txm#6
Txs#6
Rxm#6
Rxs#6
VPOS
4/10
Page 5
STM7E1A
DECODING OF FUNCTIONAL M ODE 1 (MODE = L)
Main SwitchesSc lowa closed, b openMain port is connected to the line
Sc higha open, b closedSpare port is connected to the line
Auxiliary
Switches
When closing the main port local loop (Lm high), it is externalsystemresponsibilityto ensurethatthe main
port has previously been disconnected from the line (Sc has to be high). There is no internal mechanism
to ensure this.
When closing the spare port local loop (Ls high), it is external system responsibility to ensure that the
spare port has previously been disconnected from the line (Sc has to be high). There is no internal
mechanism to ensure this.
DECODING OF FUNCTIONAL M ODE 2 (MODE = H)
C = Closed
O=Open
Lm lowd openMain port local loop open
Lm highd closedMain port local loop closed
Ls lowc openSpare port local loop open
Ls highc closedSpare port local loop closed
INPUTOUTPUTS
TEST/SnA_TXB_TX
LOC
HCO
INPUTSOUTPUTS
ScLmLsA_RXB_RXcd
LLLCCOO
LLHCOCO
LHLOCOC
LHHCOOO
HL LOCOO
C = Closed
O=Open
TEST MODE DESCRIPTION (M ODE = 0, TEST = 1)
In order to test the main switches (4-point measurement), test modes are foreseen where the main
switches can be controlled independently from each other. One can en ter in test mode by controlling the
Sc, Lm and Ls pins according to the f ollowing table.
The digital part and auxiliary switches can be tested in functional mode.
Note 1: Although there isaninternal pull down in the TEST pin, an external hardware connection from TEST to GND isrequired onthe board
to work in functional, mode.
HHH
LHH
5/10
Page 6
STM7E1A
ABSOLUTE M AX IMUM RATINGS
SymbolDescriptionMinMaxUnit
V
GND
V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
RECOMMENDED OPERATING CONDITIONS
SymbolParameterMinTYPMaxUnit
V
POS
V
NEG
T
amb
T
I
peak,
switch
C
Positive Power Supply VoltageV
POS
Reference GroundV
Input Voltage for Digital Inputs and Analog Input/Output
IN
Pins
Positive Power Supply Voltage
Negative Power Supply Voltage
Ambient Temperature
Junction Temperature
J
Admissible peak Current in 1 Switch
Load Capacitance on ASIC output
Ia
- 0.3V
NEG
- 0.3V
NEG
- 0.3V
V
NEG
NEG
NEG
NEG
+7
+7
+7
3.3 - 5%3.3 + 5%V
-3.3 - 5%-3.3 + 5%V
-2585°C
-25120°C
300mA
70pF
V
V
V
DIGITAL PART SPECIFICATIONS
SymbolParameter
Low Input Level00.8V
IL
High Input Level2V
IH
Low-High Switching Threshold Voltage1.6V
IT
Input Leakage Current-33
V
I
V
V
leak
Value
Min.Typ.Max.
POS
Unit
V
6/10
Page 7
STM7E1A
ANALOG PART SPECIFICATIONS
SymbolParameterTest Condition
Min.Typ.Max.
(1)
R
ON(main)
R
ON(aux)
∆R
ON(main)
∆R
ON(main)
(1,2)
Roff
(3)
C
pin
A
peak,signal
(1,4)
f
signal
Cross-talk
On-resistance of the main
switches
(1)
On-resistance of the
auxiliary switches
(1)
Difference of RONbetween
VIN=2V,TA= 25°C0.5Ω
devices
(1)
Difference of RONbetween
VIN=2V,TA= 25°C0.8Ω
switches of the same device
Off-resistance of the main
100kΩ
and auxiliary switches
Capacitance at any switch
pin, switch ON
(1)
Peak amplitude of the signal
-33V
at switch pins
Frequency of the signal at
5012000KHz
switch pins (3dB bandwidth)
(1,5)
Cross-talk between lines48mV
tSwitch time of the main
switches (a and b)
NOTE 1: all the parameters are valid only with a 75 Ω (±5%) load to GND.
NOTE 2: measured with a 5V DC voltage applied to a closed switch.
NOTE 3: not tested in production.
NOTE 4: measured with a 2Vpp signal.
NOTE 5: measured with the line connected to GND at one side with a 75
signal.
NOTE 6: during the switching between the main and spare ports, the behaviour of the component is not guaranteed: both main switches can
be open (break before make).
NOTE 7: measured with the line switching from a 2.5V DC level (main or spare port) to a -2.5V DC level (spare or main port).
Ω resistorand all the otherlinesdrivenby a1MHz,2Vppsinewave
Value
Unit
1.62Ω
5075Ω
50120pF
p
rms
0.151µs
CURRENT CONSUMPTION SPECIFICATIONS
SymbolParameter
(1)
P
main
(1)
P
aux
I
STDBY(VNEG)
I
STDBY(VPOS)
E
SWITCH(VNEG)
E
SWITCH(VPOS)
NOTE 1: these parameters are not tested in production.
NOTE 2: this power is not delivered by V
NOTE 3: only valid with digital inputs to GND or V
Maximal average power dissipation in the main
switches
Maximal average power dissipation in the auxiliar
switches
(1,3)
Standby (no switching) current of VNEG-500500µA
(1,3)
Standby (no switching) current of VPOS-500500µA
(1)
Energy to be delivered to by VPOS when switching-100100nJ
(1)
Energy to be delivered to by VPOS when switching-100100nJ
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibilit y for t he
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
systems without express written approval of STMicroelectronics.
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