Datasheet STM6717, STM6718, STM6719, STM6720, STM6777 Datasheet (ST)

Features

STM6717/6718/6719/6720
STM6777/6778/6779/6780

Dual/triple ultra-low voltage supervisors

with push-button reset (with delay option)

■ Primary supply (V

) monitor.

CC1

Fixed (factory-programmed) reset thresholds:

4.63 V to 1.58 V

■ Secondary supply (V

) monitor

CC2

(STM6717/18/19/20/77/78)

■ Fixed (factory-programmed) reset thresholds:

3.08 V to 0.79 V

■ Tertiary supply monitor (using externally

adjustable RSTIN): 0.626 V internal reference

■ RST outputs (push-pull or open drain); state

guaranteed if V

■ Reset delay time (t

CC1

or V

rec

≥ 0.8 V

CC2

) on power-up: 13.2 ms,

210 ms, 900 ms (typ)

■ Manual reset input (MR)

■ Optional delayed manual reset input (MRC)

with external capacitor (STM6777/78/79/80)

■ Low supply current - 11 µA (typ),

V

= V

CC1

■ Operating temperature: –40 °C to 85 °C

CC2

= 3.6 V

(industrial grade)

Table 1. Device summary

SOT23-5 (WY)

SOT23-6 (WB)

Monitored voltages

Part

number

STM6717 ✔✔ ✔ ✔ WY

STM6718 ✔✔ ✔ ✔ WY

STM6719 ✔✔✔ ✔ ✔ WB

STM6720 ✔✔✔ ✔ ✔ WB

STM6777 ✔✔ ✔ ✔ ✔ WB

STM6778 ✔✔ ✔ ✔ ✔ WB

STM6779 ✔✔✔✔ ✔WB

STM6780 ✔✔✔✔✔ WB

August 2011 Doc ID 11469 Rev 8 1/30

V

CC1

V

CC2

RSTIN

Manual reset

input (MR)

Delayed MR

pin (MRC)

Reset output (RST

Active-low

(push-pull)

(open drain)

)

Active-low

Package

www.st.com

1

Contents STM6717/6718/6719/6720/STM6777/6778/6779/6780

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80 . . . . . . . . 7

1.1.2 Active-low, open drain reset output (RST

1.1.3 Push-button reset input (MR

1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80) . . . . . . . . . . . . . . 8

1.1.5 Primary supply voltage monitoring input (V

1.1.6 Secondary supply voltage monitoring input (V

1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80) . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

) - STM6717/19/77/79 . . . . . . . 7

) . . . . . . . . . . . . . . . . . . . 8

CC1

) . . . . . . . . . . . . . . . . . 8

CC2

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. t

Table 8. SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 23

Table 9. SOT23-6 – 6-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24

Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MLMH

Doc ID 11469 Rev 8 3/30

List of figures STM6717/6718/6719/6720/STM6777/6778/6779/6780

List of figures

Figure 1. Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 11. STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12. Ensuring RST
Figure 13. Supply current vs. temperature (V
Figure 14. Supply current vs. temperature (V
Figure 15. Supply current vs. temperature (V
Figure 16. Supply current vs. temperature (V
Figure 17. Normalized V
Figure 18. Maximum V
Figure 19. Normalized V
Figure 20. Normalized V

Figure 21. Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 22. V

-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC1

Figure 23. Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 24. MR

-to-reset output delay vs. temperature (V

Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 26. MR
Figure 27. MR

timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23

Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 24

Figure 30. Carrier tape for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

valid to VCC = 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10

= 5.5 V; V

CC1

= 3.6 V; V

CC1

= 3.0 V; V

CC1

= 2.0 V; V

reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC

transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13

CC

threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RST1

threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RST2

CC1

CC1

= 3.6 V) . . . . . . . . . . . . . . . . . . . . . . 11

CC2

= 2.75 V) . . . . . . . . . . . . . . . . . . . . . 11

CC2

= 2.0 V) . . . . . . . . . . . . . . . . . . . . . . 12

CC2

= 1.0 V) . . . . . . . . . . . . . . . . . . . . . . 12

CC2

= 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description

1 Description

The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/low­supply current processor (micro or DSP) supervisors, designed to monitor two (or three)
system power supply voltages. They are targeted at applications such as set-top boxes
(STBs), portable, battery-powered systems, networking, and communication systems.

All device options have a push-button-type manual reset input (MR

). The
STM6777/78/79/80 also includes an option which enables the user to delay the start of the
manual reset process from 6 µs (MRC pin left open) or more with external capacitor. The
delay is implemented by connecting the appropriately sized capacitor between the MRC pin
and V

Two of the three supplies monitored (V
factory-trimmed) thresholds (V

(typical 4 s delay with a 3.3 µF capacitor, see Table 7 on page 21).

SS

RST1

CC1

and V

and V

RST2

) have fixed (customer-selectable,

CC2

). The third voltage is monitored using an

externally adjustable RSTIN threshold (0.626 V internal reference).

If any of the three monitored voltages drop below its factory-trimmed or adjustable
thresholds, or if MR
RST

is maintained at low for a minimum delay period (t
their respective thresholds and MR
the correct reset output logic state when V

is asserted to logic low, a RST is asserted (driven low). Once asserted,

) after ALL supplies rise above

rec

returns to high. These devices are guaranteed to be in

CC1

and/or V

is greater than 0.8 V.

CC2

These devices are available in standard 5-pin or 6-pin SOT23 packages (see Tab le 1 o n

page 1).

Doc ID 11469 Rev 8 5/30

Description STM6717/6718/6719/6720/STM6777/6778/6779/6780

Figure 1. Logic diagram (STM6717/18) Figure 2. Logic diagram (STM6777/78)

V

V

CC1

CC2

V

V

CC1

CC2

MRC

MR

STM6777
STM6778

V

SS

RST

MR

STM6717
STM6718

V

SS

RST

AI10413

Figure 3. Logic diagram (STM6719/20) Figure 4. Logic diagram (STM6779/80)

V

CC

STM6779
STM6780

V

SS

RST

RSTIN

MR

V

CC2

STM6719
STM6720

V

SS

V

CC1

RSTIN

RST

AI10414

MRC

MR

AI10415

AI10416

Table 2. Signal names

MR Push-button reset input

MRC Manual reset delay input

RST Active-low reset output

V

CC1

V

CC2

RSTIN Adjustable reset comparator input

V

SS

6/30 Doc ID 11469 Rev 8

Primary supply voltage input

Secondary supply voltage input

Ground

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description

Figure 5. STM6717/18 SOT23-5 connections Figure 6. STM6777/78 SOT23-6 connections

V

RST

V

SS

MR

SS

1

2

3

V

1

2

3

5

CC1

V

4

CC2

RST

V

MR

6

CC1

5

MRC

V

4

CC2

AI10417

AI10418

Figure 7. STM6719/20 SOT23-6 connections Figure 8. STM6779/80 SOT23-6 connections

RST

V

SS

MR

V

1

2

3

6

5

CC1

RSTIN

V

4

CC2

AI10419

RST

V

MR

SS

1

2

3

V

6

CC1

RSTIN

5

MRC

4

AI10420

1.1 Pin descriptions

1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80

The RST pin is driven low and stays low whenever V
factory-trimmed or adjustable reset threshold or when MR
for t

after ALL supply voltages being monitored rise above their reset thresholds and MR

rec

goes from low to high. (Push-pull outputs are referenced to V

CC1

or V

or RSTIN falls below its

CC2

goes to logic low. It remains low

.)

CC1

1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79

The RST pin is driven low and stays low whenever V
factory-trimmed or adjustable reset threshold or when MR
for t

after ALL supply voltages being monitored rise above their reset thresholds and MR

rec

goes from low to high. Connect an external pull-up resistor to V
should be sufficient for most applications.

CC1

or V

or RSTIN falls below its

CC2

goes to logic low. It remains low

. A 10 kΩ pull-up resistor

CC1

1.1.3 Push-button reset input (MR)

When MR goes low the RST output is driven low. RST remains low as long as MR is low and
for t

after MR returns to high. This active-low input has an internal 50 kΩ pull-up resistor to

rec

Doc ID 11469 Rev 8 7/30

Description STM6717/6718/6719/6720/STM6777/6778/6779/6780

V

. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs,

CC1

or connected to V

Connect a normally open momentary switch from MR
not required. (If MR
connecting a 0.1µF capacitor from MR

through a switch. If unused, leave this pin open or connect it to V

SS

CC1

to VSS; external debounce circuitry is

is driven from long cables or if the device is used in noisy environments,

to VSS provides additional noise immunity.

.

1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80)

This pin is either left open or connected to VSS via a capacitor. By selecting the appropriate
capacitor, the manual reset process, initiated by pressing the push-button manual reset
input, can be delayed by any value from 6 µs or more (see Table 7 on page 21).

1.1.5 Primary supply voltage monitoring input (V

CC1

)

It also is the input for the primary reset threshold monitor. Available fixed (customer­selectable, factory-programmed) reset thresholds include 4.63 V to 1.58 V.

1.1.6 Secondary supply voltage monitoring input (V

CC2

)

This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable,
factory-programmed) reset thresholds include 3.08 V to 0.79 V.

1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80)

This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls
below 0.626 V (internal reference voltage at this comparator). The monitored voltage reset
threshold is set with an external resistor-divider network.

Table 3. Pin functions

Pin

STM6717

STM6718

1111RST

3333MR

— — 5 4 MRC Manual reset delay input

STM6719

STM6720

STM6777

STM6778

STM6779

STM6780

Name Function

Active-low reset output

Push-button reset input

5666V

444—V

— 5 — 5 RSTIN Adjustable reset comparator input

2222V

8/30 Doc ID 11469 Rev 8

Primary supply voltage input

CC1

Secondary supply voltage input

CC2

Ground

SS

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description

Figure 9. Block diagram

V

V

CC2

RSTIN

CC1

V

(1)

V

(2)

V

= 0.626

V

CC1

REF/2

RST1

RST2

COMPARE

COMPARE

COMPARE

t

rec

Generator

RST

Logic

1. V

MR

(3)

MRC

input is available on STM6717/18/19/20/77/78.

CC2

2. RSTIN available only on STM6719/20/79/80.

3. MRC available only on STM6777/78/79/80.

Figure 10. Hardware hookup

From DC/DC Converter

V

CC2

V

CC3

=

(626.5mV)

R1 + R2

(

)

R2

V

CC3

0.1µF

R1

R2

Push-button

Switch

AI10421

(1)

V

CC1

V

CC1

0.1µF

C

V

CC2

RSTIN

MR

MRC

STM67xx

(2)

RST RST (To Processor Reset)

(3)

V

SS

1. V

is available only on STM6717/18/19/20/77/78.

CC2

2. RSTIN available only on STM6719/20/79/80.

3. MRC available only on STM6777/78/79/80.

Doc ID 11469 Rev 8 9/30

AI10422

Operation STM6717/6718/6719/6720/STM6777/6778/6779/6780

2 Operation

2.1 Applications information

1. Interfacing to processors with bi-directional reset pins

Most processors with bi-directional reset pins can interface directly to the open drain
RST

outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST
output and a bi-directional reset interface can be in logic contention. To prevent this
contention, connect a 4.7 kΩ resistor between RST
shown in Figure 11.

2. Ensuring a valid RST

output down to VCC=0 V

The STM67xx supervisors are guaranteed to be in the correct RST
when V
levels down to V

and/or V

CC1

is greater than 0.8 V. In applications which require valid reset

CC2

= 0, a pull-down resistor to active-low outputs (push-pull only, see

CC

Figure 12) will ensure that the reset line is valid while the reset output can no longer

sink or source current. This scheme does NOT work with the open drain outputs of the
STM6717/19/77/79.

The resistor value used is not critical, but it must be large enough not to load the reset
output when V

is above the reset threshold. For most applications, 100 kΩ is

CC

adequate.

and the processor’s reset I/O as

output logic state

Figure 11. STM67xx interface to processor with bi-directional reset pins

V

CC2

Figure 12. Ensuring RST

V

CC1

V

CC1

V

CC2

STM67xx

V

SS

RST

To other

system

components

4.7kΩ

Processor

RESET

V

SS

valid to VCC = 0 (active-low, push-pull outputs)

STM67xx

V

CC1

V

CC1

RST

V

SS

R1

AI10425

10/30 Doc ID 11469 Rev 8

AI10426

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics

3 Typical operating characteristics

Note: Typical values are at TA = 25 °C unless otherwise noted.

Figure 13. Supply current vs. temperature (V

18

16

14

12

10

8

6

Supply current (µA)

4

2

0

–40 –20 0 20 40 60 80

I

TOTAL

I

CC1

I

CC2

Temperature (°C)

Figure 14. Supply current vs. temperature (V

18

= 5.5 V; V

CC1

= 3.6 V; V

CC1

= 3.6 V)

CC2

= 2.75 V)

CC2

AI11843

16

14

12

10

8

6

Supply current (µA)

4

2

0

–40 –20 0 20 40 60 80

I

TOTAL

I

CC1

I

CC2

Temperature (°C)

AI11844

Doc ID 11469 Rev 8 11/30

Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780

Figure 15. Supply current vs. temperature (V

18

16

14

12

10

I

8

6

Supply current (µA)

4

2

0

–40 –20 0 20 40 60 80

TOTAL

I

CC1

I

CC2

Temperature (°C)

Figure 16. Supply current vs. temperature (V

18

= 3.0 V; V

CC1

= 2.0 V; V

CC1

CC2

CC2

= 2.0 V)

AI11845

= 1.0 V)

16

14

12

10

8

6

Supply current (µA)

4

2

0

–40 –20 0 20 40 60 80

I

TOTAL

I

CC1

I

CC2

Temperature (°C)

AI11846

12/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics

Figure 17. Normalized VCC reset time-out period vs. temperature

1.07

1.05

1.03

1.01

Reset period

0.99

0.97
–40 –20 0 20 40 60 80

Temperature (°C)

AI11847

Figure 18. Maximum V

1000

100

transient duration (µs)

10

CC

Maximum V

1

1 10 100 1000

transient duration vs. reset threshold overdrive

CC

Reset threshold overdrive (mV)

AI11848

Doc ID 11469 Rev 8 13/30

Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780

Figure 19. Normalized V

1.004

1.002

1.000

reset threshold

RST1

0.998

V

0.996
–40 –20 0 20 40 60 80

Figure 20. Normalized V

1.004

threshold vs. temperature

RST1

Temperature (°C)

threshold vs. temperature

RST2

AI11849

1.002

1.000

reset threshold

RST2

0.998

V

0.996
–40 –20 0 20 40 60 80

Temperature (°C)

AI11850

14/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics

Figure 21. Reset input threshold vs. temperature

630

629

628

627

626

Reset input threshold (mV)

625

624

–40 –20 0 20 40 60 80

Temperature (°C)

AI11851

Figure 22. V

-to-reset delay (µs)

CC1

V

-to-reset delay vs. temperature

CC1

48

44

40

36

32

28

–40 –20 0 20 40 60 80

Temperature (°C)

AI11852

Doc ID 11469 Rev 8 15/30

Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780

Figure 23. Reset input-to-reset output delay vs. temperature

29.0

28.5

28.0

27.5

27.0

26.5

26.0

25.5

RSTIN-to-reset output delay (µs)

25.0
–40 –20 0 20 40 60 80

Temperature (°C)

AI11853

Figure 24. MR

MR-to-reset output delay (ns)

-to-reset output delay vs. temperature (V

500

480

460

440

420

400

–40 –20 0 20 40 60 80

CC1

= 3.6V)

Temperature (°C)

AI11854

16/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Maximum rating

4 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

T

STG

T

SLD

V

IO

V

CC1, VCC2

I

IO

Storage temperature (VCC off) –55 to 150 °C

(1)

Lead solder temperature for 10 seconds 260 °C

Input or output voltage

–0.3 to V

–0.3 to V

CC1

CC2

Supply voltage –0.3 to 7.0 V

Input or output current (all pins) 20 mA

SOT23-5 654 mW

P

D

1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.

Power dissipation

SOT23-6 675 mW

+ 0.3 V

+ 0.3 V

Doc ID 11469 Rev 8 17/30

DC and AC parameters STM6717/6718/6719/6720/STM6777/6778/6779/6780

5 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in

Table 5: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.

Table 5. Operating and AC measurement conditions

Parameter STM67xx Unit

V

supply voltage 0.8 to 5.5 V

CC

Ambient operating temperature (T

Input rise and fall times ≤ 5ns

Input pulse voltages 0.2 to 0.8V

Input and output timing ref. voltages 0.3 to 0.7V

) –40 to 85 °C

A

CC

CC

V

V

Figure 25. AC testing input/output waveforms

0.8V

CC

0.2V

CC

Figure 26. MR

MR

RST

Figure 27. MR

MR

RST

timing waveform (STM6717/18/19/20)

t

MLMH

t

MLRL

t

rec

timing waveform (STM6777/78/79/80)

(1)

t

MLMH

t

MLRL

0.7V

0.3V

CC

CC

AI02568

AI10423a

1. By connecting a certain capacitor between the MRC pin and VSS, the RST can be delayed from 6 µs or
more (t

, see Table 7 on page 21).

MLMH

18/30 Doc ID 11469 Rev 8

t

rec

AI10424c

STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters

Table 6. DC and AC characteristics

Sym

V

CC

I

CC1

I

CC2

(2)

I

LI

I

LO

V

OL

V

OH

Alter-

native

Description Test condition

Operating voltage 0.8 5.5 V

V

supply current

CC1

V

supply current

CC2

Input leakage current 0 V = VIN = V

Open drain RST output

leakage current

Output low voltage (RST;

push-pull or open drain)

Output high voltage (RST;

push-pull only)

(1)

V

< 5.5 V, all I/O pins open 12 35 µA

CC1

V

< 3.6 V, all I/O pins open 8 23 µA

CC1

V

< 3.6 V, all I/O pins open 3 9 µA

CC2

< 2.75 V, all I/O pins open 2.5 7 µA

V

CC2

CC

> V

V

CC1

RST

V

CC1

= 1 µA, RST asserted

I

SINK

V

CC1

= 50 µA, RST asserted

I

SINK

V

CC1

= 100 µA, RST asserted

I

SINK

V

CC1

= 1.2 mA, RST asserted

I

SINK

V

CC1

= 3.2 mA, RST asserted

I

SINK

≥ 1.8 V, I

V

CC1

RST

V

≥ 2.7 V, I

CC1

, V

RST1

CC2

not asserted

or V

or V

or V

or V

or V

≥ 0.8 V,

CC2

≥ 1.0 V,

CC2

≥ 1.2 V,

CC2

≥ 2.7 V,

CC2

≥ 4.5 V,

CC2

SOURCE

not asserted

SOURCE

> V

RST2

= 200 µA,

= 500 µA,

RST not asserted

Min Typ Max Unit

–1 +1 µA

;

0.8V

CC1

0.8V

CC1

0.5 µA

0.3 V

0.3 V

0.3 V

0.3 V

0.4 V

V

V

(3)

t

R

Reset thresholds

(4)

V

RST

V

TH1

Push-pull RST rise time

(STM6718/20/78/80)

V

reset threshold

CC1

V

≥ 4.5 V, I

CC1

RST not asserted

SOURCE

= 800 µA,

0.8V

CC1

V

Rise time measured from 10% to

90% of VCC;

525ns

CL = 5 pF, VCC = 3.3 V

L (falling) 4.500 4.625 4.750 V

M (falling) 4.250 4.375 4.500 V

T (falling) 3.000 3.075 3.150 V

S (falling) 2.850 2.925 3.000 V

R (falling) 2.550 2.625 2.700 V

Z (falling) 2.250 2.313 2.375 V

Y (falling) 2.125 2.188 2.250 V

W (falling) 1.620 1.665 1.710 V

V (falling) 1.530 1.575 1.620 V

Doc ID 11469 Rev 8 19/30

DC and AC parameters STM6717/6718/6719/6720/STM6777/6778/6779/6780

Table 6. DC and AC characteristics (continued)

V

V

Sym

RST2

HYST

t

RD

(4)

Alter-

native

V

TH2

Description Test condition

T (falling) 3.000 3.075 3.150 V

S (falling) 2.850 2.925 3.000 V

R (falling) 2.550 2.625 2.700 V

Z (falling) 2.250 2.313 2.375 V

Y (falling) 2.125 2.188 2.250 V

W (falling) 1.620 1.665 1.710 V

V (falling) 1.530 1.575 1.620 V

V

reset threshold

CC2

I (falling) 1.350 1.388 1.425 V

H (falling) 1.275 1.313 1.350 V

G (falling) 1.080 1.110 1.140 V

F (falling) 1.020 1.050 1.080 V

K (falling) 0.895 0.925 0.955 V

J (falling) 0.845 0.875 0.905 V

E (falling) 0.810 0.833 0.855 V

D (falling) 0.765 0.788 0.810 V

Reset threshold hysteresis Referenced to V

VCC to RST delay

V

V

CC1

CC2

= (V

(V

= (V
(V

RST1

– 100 mV)

RST

RST2

– 75 mV)

RST2

+ 100 mV) to

blank 140 210 280

(1)

typical 0.5 %

RST

Min Typ Max Unit

20 µs

+ 75 mV) to

20 µs

t

rec

t

RP

RST pulse width

G 600 900 1200

Adjustable reset comparator input (STM6719/20/79/80)

V

RSTIN

I

RSTIN

RSTIN input threshold 611 626.5 642 mV

RSTIN input current –25 +25 nA

RSTIN hysteresis 3 mV

t

RSTIND

RSTIN to RST

output delay

V

RSTIN

to (V

RSTIN

20/30 Doc ID 11469 Rev 8

msB 8.8 13.2 17.6

– 30 mV) 22 µs

STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters

Table 6. DC and AC characteristics (continued)

Sym

Alter-

native

Description Test condition

Manual (push-button) reset input

V

IL

V

IH

MR input voltage

MR minimum pulse width

(STM6717/18/19/20)

t

MLMH

t

MR

MR minimum pulse width

MRC connected via

(STM6777/78/79/80)

t

MLRLtMRD

MR to RST output delay 200 ns

MR

glitch immunity

(STM6717/18/19/20)

MR

pull-up resistance 25 50 80 kΩ

1. Valid for ambient operating temperature: TA = –40 to 85 °C; V
noted).

2. Input leakage for the MRC pin is not tested.

3. Guaranteed by design.

4. The leakage current measured on the RST

pin is tested with the reset de-asserted (output high impedance).

capacitor to V

= 0.8 to 5.5 V and V

CC1

SS

(1)

Min Typ Max Unit

0.3V

C

V

V

0.7V

C1

CC1

1µs

6µs

100 ns

= 0.8 to 3.6 V (except where

CC2

CC1

minimum pulse width

MLMH

Capacitor value

(1)

Table 7. t

V

100 pF 0.1 µF 2.2 µF 3.3 µF 4.7 µF 6.8 µF

1.6 V 120 µs 120 ms 2.6 s 4.0 s 5.6 s 8.2 s

2.0 V 122 µs 122 ms 2.7 s 4.0 s 5.8 s 8.3 s

3.0 V 125 µs 125 ms 2.7 s 4.1 s 5.9 s 8.5 s

4.0 V 128 µs 129 ms 2.8 s 4.2 s 6.0 s 8.7 s

5.0 V 130 µs 130 ms 2.8 s 4.3 s 6.1 s 8.8 s

1. At 25 °C (typical)

Doc ID 11469 Rev 8 21/30

Package mechanical data STM6717/6718/6719/6720/STM6777/6778/6779/6780

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

22/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data

Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing

5x b

Datum A

0.20

Note: Drawing is not to scale.

Table 8. SOT23-5 – 5-lead small outline transistor package mechanical data

Symb

Min Typ Max Min Typ Max

A——1.45——0.057

A1 — — 0.15 — — 0.006

A2 0.90 1.15 1.30 0.035 0.045 0.051

E

1

e

M

0.20

CAB

B

E1

e1

D

A

C

θ

L

C 0.10

A1

5x

C

A2

A

0133778

mm inches

b 0.30 — 0.50 0.012 — 0.020

C 0.08 — 0.22 0.003 — 0.009

D — 2.90 — — 0.114 —

E — 2.80 — — 0.110 —

E1 — 1.60 — — 0.063 —

e — 0.95 — — 0.037 —

e1 — 1.90 — — 0.075 —

L 0.30 0.45 0.60 0.012 0.018 0.024

Q0°4°8°0°4°8°

N5 5

Note: Dimensions per JEDEC SOT/SOP product outline MO-178C, variation AA

Doc ID 11469 Rev 8 23/30

Package mechanical data STM6717/6718/6719/6720/STM6777/6778/6779/6780

Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing

e1

Datum A

Note: Drawing is not to scale.

Table 9. SOT23-6 – 6-lead small outline transistor package mechanical data

Symb

Min Typ Max Min Typ Max

A——1.45——0.057

A1 — — 0.15 — — 0.006

6x b

0.10 C A B

0.20

B

E

1

M

E1

e

D

A

C

θ

L

0.10C

A1

6x

C

mm inches

A2

A

7049714

A2 0.90 1.15 1.30 0.035 0.045 0.051

b 0.30 — 0.50 0.012 — 0.020

C 0.08 — 0.22 0.003 — 0.009

D — 2.90 — — 0.114 —

E — 2.80 — — 0.110 —

E1 — 1.60 — — 0.063 —

e — 0.95 — — 0.037 —

e1 — 1.90 — — 0.075 —

L 0.30 0.45 0.60 0.012 0.018 0.024

Q0°4°8°0°4°8°

N6 6

Note: Dimensions per JEDEC SOT/SOP product outline MO-178C variation AB

24/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data

Figure 30. Carrier tape for SOT23-5L and SOT23-6L

P

D

T

A

TOP COVER

TAPE

K

0

0

CENTER LINES
OF CAVITY

P

2

B

0

0

P

1

E

F

W

USER DIRECTION OF FEED

AM03073v1

Note: Part pin 1 indicator is on bottom left for shipping method “F” and is on top right for shipping

method “R” see Section 7.

Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L

Package W D E P

SOT23-5
SOT23-6

8.00

+0.30/

–0.10

1.50

+0.10/

–0.00

1.75

±0.10

4.00

±0.10

P

0

2.00

±0.10

FA0B

2

3.50

±0.05

3.23

±0.10

0

3.17

±0.10

K

0

1.37

±0.10

P

1

4.00

±0.10

TUnit

0.254

±0.013

Bulk

Qty

mm 3000

Doc ID 11469 Rev 8 25/30

Part numbering STM6717/6718/6719/6720/STM6777/6778/6779/6780

7 Part numbering

Table 11. Ordering information scheme

Example: STM67xx LT WY 6 F

Device type

STM67xx

Reset thresholds (V

STM6717/18/19/20/77/78 (V

Suffix V

LT 4.625 3.075 L–
MS 4.375 2.925 T–
MR 4.375 2.625 S–

(1)

TZ

(1)

TW

TI 3.075 1.388 R– 2.625

(1)

TG

and V

RST1

RST1

RST1

3.075 2.313 Y–

3.075 1.665 V–

RST2

and V

V

) for V

CC1

) STM6779/80 (V

RST2

RST2

and V

CC2

Suffix V

(1)

(1)

(1)

(1)

(1)

RST1

4.625

3.075

2.925

2.188

1.575

3.075 1.110 Z– 2.313

RST1

only)

TK 3.075 0.925

TE 3.075 0.833
SY
SV
SH

SF
SJ

SD

(1)

(1)

(2)

(1)

(3)

(3)

2.925 2.188

2.925 1.575

2.925 1.313

2.925 1.050

2.925 0.875

2.925 0.788

YV 2.188 1.575

YH 2.188 1.313

YF 2.188 1.050

YJ 2.188 0.875

YD 2.188 0.788
VH 1.575 1.313

VF 1.575 1.050

VJ 1.575 0.875

VD 1.575 0.788

Reset pulse width

blank: t
B: t
G: t

= 140 ms to 280 ms

rec

= 8.8 ms to 17.6 ms

rec

= 600 ms to 1200 ms

rec

Package

WY = SOT23-5
WB = SOT23-6

Temperature range

6 = –40 to 85°C

Shipping method

®

E = ECOPACK
F = ECOPACK

(4)

= ECOPACK® package, tape and reel (pin 1 at top right).

R

1. T

hese are standard versions and are typically held in stock. A non-standard version may require a higher minimum volumes, and/or longer

delivery times. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.

2. Available in STM6719 version only.

3. Available in STM6717 version only.

4. Available for STM6720SY, STM6719SF and STM6719SFB versions only.

package, tubes

®

package, tape and reel

26/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Part numbering

Table 12. Marking description

Part number V

threshold (V) V

RST1

threshold (V) Topside marking Bottomside marking

RST2

STM6717SD 2.925 0.788 7SD1 PYWW

STM6717SJ 2.925 0.875 7SJ1 PYWW

STM6717SF 2.925 1.050 7SF1 PYWW

STM6717TG 3.075 1.110 7TG1 PYWW

STM6717TGG 3.075 1.110 7TG9 PYWW

STM6717TW 3.075 1.665 7TW1 PYWW

STM6717SV 2.925 1.575 7SV1 PYWW

STM6717SY 2.925 2.188 7SY1 PYWW

STM6717TZ 3.075 2.313 7TZ1 PYWW

STM6718SF 2.925 1.050 7SF2 PYWW

STM6718TG 3.075 1.110 7TG2 PYWW

STM6718TW 3.075 1.665 7TW2 PYWW

STM6718SV 2.925 1.575 7SV2 PYWW

STM6718SY 2.925 2.188 7SY2 PYWW

STM6718TZ 3.075 2.313 7TZ2 PYWW

STM6719SF 2.925 1.050 7SF3 PYWW

STM6719SFB 2.925 1.050 7SFB PYWW

STM6719TG 3.075 1.110 7TG3 PYWW

STM6719SH 2.925 1.313 7SH3 PYWW

STM6719TW 3.075 1.665 7TW3 PYWW

STM6719SV 2.925 1.575 7SV3 PYWW

STM6719SY 2.925 2.188 7SY3 PYWW

STM6719TZ 3.075 2.313 7TZ3 PYWW

STM6720SF 2.925 1.050 7SF4 PYWW

STM6720TG 3.075 1.110 7TG4 PYWW

STM6720TW 3.075 1.665 7TW4 PYWW

STM6720SV 2.925 1.575 7SV4 PYWW

STM6720SY 2.925 2.188 7SY4 PYWW

STM6720TZ 3.075 2.313 7TZ4 PYWW

STM6777SF 2.925 1.050 7SF5 PYWW

STM6777TG 3.075 1.110 7TG5 PYWW

STM6777TW 3.075 1.665 7TW5 PYWW

STM6777SV 2.925 1.575 7SV5 PYWW

STM6777SY 2.925 2.188 7SY5 PYWW

STM6777TZ 3.075 2.313 7TZ5 PYWW

Doc ID 11469 Rev 8 27/30

Part numbering STM6717/6718/6719/6720/STM6777/6778/6779/6780

Table 12. Marking description (continued)

Part number V

STM6778SF 2.925 1.050 7SF6 PYWW

STM6778TG 3.075 1.110 7TG6 PYWW

STM6778TW 3.075 1.665 7TW6 PYWW

STM6778SV 2.925 1.575 7SV6 PYWW

STM6778SY 2.925 2.188 7SY6 PYWW

STM6778TZ 3.075 2.313 7TZ6 PYWW

STM6779L 4.625 — 7Lx7 PYWW

STM6779T 3.075 — 7Tx7 PYWW

STM6779S 2.925 — 7Sx7 PYWW

STM6779Y 2.188 — 7Yx7 PYWW

STM6779V 1.575 — 7Vx7 PYWW

STM6780L 4.625 — 7Lx8 PYWW

STM6780T 3.075 — 7Tx8 PYWW

STM6780S 2.925 — 7Sx8 PYWW

STM6780Y 2.188 — 7Yx8 PYWW

STM6780V 1.575 — 7Vx8 PYWW

threshold (V) V

RST1

threshold (V) Topside marking Bottomside marking

RST2

Note: For topside marking, “7” is the family number, followed by the V

threshold and device number (1,9 = STM6717, 2 = 6718, 3 = 6719, 4 = 6720, 5 = 6777,
6 = 6778, 7 = 6779, 8 = 6780).

For bottomside marking, “P” = assembly site, “Y” = 1-digit year, and “WW” = 2-digit work
week.

threshold, V

RST1

RST2

28/30 Doc ID 11469 Rev 8

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Revision history

8 Revision history

Table 13. Document revision history

Date Revision Changes

18-Oct-2004 1 First draft

25-Oct-2004 1.1 Descriptive text, sales types (Ta bl e 1 1 )

14-Jan-2005 1.2 Update characteristics, pin functions (Ta bl e 2 )

09-Feb-2005 1.3 Update characteristics (Figure 9; Tab le 3 )

08-Apr-2005 1.4

28-Jul-2005 1.5 Update characteristics, reset delay (Figure 10, 27; Tab l e 4 , 6, 7, 11)

13-Sep-2005 2

07-Oct-2005 3 Marked STM6779/6780 as availability request parts (Ta b l e 1 , 11)

07-Feb-2007 4 Updated STM6779/6780 availability (cover page, Ta b le 1 , 11)

12-Jun-2007 5 Updated Ta bl e 1 1 , added Table 12: Marking description.

05-Dec-2007 6 Updated cover page, Ta bl e 6 ,

22-Mar-2010 7

02-Aug-2011 8 Removed footnote from Table 6: DC and AC characteristics.

Update characteristics and mechanical dimensions; add table
(Figure 9, 10, 27, 28, 29; Ta bl e 4 , 6, 11, 8, 9)

Add operating characteristics; update timings, document status, Lead­free text (Figure Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,

26, 27; Ta bl e 1 1 )

11, and 12.

Updated Features; Ta bl e 6 , 8, 9, 11, 12; footnote 1 of Ta b le 4 ;

Section 6: Package mechanical data; added tape and reel

specifications (Figure 30, Ta bl e 1 0 , footnote 4 of Ta bl e 1 1 );
reformatted document.

Doc ID 11469 Rev 8 29/30

STM6717/6718/6719/6720/STM6777/6778/6779/6780

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30/30 Doc ID 11469 Rev 8