Datasheet STLVDS104BDR, STLVDS104BTR, STLVDS104BD Datasheet (SGS Thomson Microelectronics)

4-PORT LVDS AND 4-PORT TTL-TO LVDS

■ RECEIVER AND DRIVERS MEET OR

EXCEED THE REQUIREMENTS OF ANSI
EIA/TIA-644 STANDARD, RECEIVERS
DIFFERENTIAL INPUT LEVELS, ±100mV

■ DESIGNED FOR SIGNALING RATES UP TO

630Mbps

■ OPERATES FROM A SINGLE 3.3V SUPPLY

■ LOW VOLTAGE DIFFERENTIAL SIGNALING

WITH TYPICAL OUTPUT VOLTAGE OF
350mV AND A 100Ω LOAD

■ PROPAGATION DELAY TIME: 3.1ns (TYP)

■ ELECTRICALLY COMPATIBLE WITH LVDS,

PECL, LVPECL, LVTTL, LVCOMOS, GTL,
BTL, CTT, S STL, OR HSTL OUTPUTS W ITH
EXTERNAL NETWORK

■ BUS TERMINAL ESD (HBM) EXCEEDS 7KV

■ SO AND TSSOP PACKAGING

DESCRIPTION

The STL VDS 104 is a differential line receiver and
a LVTTL input connected to four differential line
drivers that implement the electrical
characteristics of low voltagedifferential signaling,
for point to point baseband data transmission over
controlled impedance media of approximately
100Ω. The trans mission media can be
printed-circuit board traces, backplanes, or cable.

STLVDS104

REPEATERS

SOP TSSOP

LVDS, as specified in EIA/TIA-644 is a data
signaling technique that offers low-power, low
noise coupling, and switching s peed to transmit
data at a speed up to 630Mbps at relatively long
distances.
The drivers integrated into t he same substra te,
along with the low pulse skew of balanced
signaling, allow extremely precise timing
alignment of the signals repeated from the input.
The device allows extremely precise timing
alignment of the signal rep eated from the input.
This is particularly advantageous in distribution or
expansion of s ignals such as clock or serial data
stream.

ORDERING CODES

Type

STLVDS104BD -40 to 85 °C SO-16 (Tube) 50parts per tube / 20tube per box
STLVDS104BDR -40to 85 °C SO-16 (Tape & Reel) 2500 parts per reel
STLVDS104BTR -40 to 85 °C TSSOP16 (Tape & Reel) 2500 parts per reel

Temperature

Range

Package Comments

1/8May 2003

STLVDS104

PIN CONFIGURATION

PIN DESCRIPTION

PlN N° SYMBOL NAME AND FUNCTION

1, 2, 3, 8 EN1 to EN4 Enable Driver Inputs

6, 7 A, B Receiver Input

9, 11, 13, 15 1Z to 4Z Driver Inputs

10, 12, 14, 16 1X to 4X Driver Inputs

5 GND Ground
4

V

CC

Supply Voltage

FUNCTIONAL DIAGRAM

FUNCTIONAL TABLE

INPUT ENABLES OUTPUTS

V

ID=VA-VB

XXZZ
XLZZ

V

≥ 100mV

ID

-100mV < V
V

ID

L=Low level, H=High Level, ?=Indeterminate, Z= High Impedance

< 100mV

ID

≤ −100mV

#EN #Y #Z

HHL
H??
HLH

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

ESD ESD Protection Voltage (HBM) Y, Z, to GND 7 KV

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal.

2/8

Supply Voltage (Note 1)

CC

Voltage Range Enable Inputs -0.5 to 6 V

R

-0.5 to 4 V

A, B, Y or Z -0.5 to 4 V

All Pins 2 KV

Storage Temperature Range

stg

-65 to +150 °C

STLVDS104

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

V

V

|V

V

T

Supply Voltage 3.0 3.3 3.6 V

CC

HIGH Level Input Voltage 2.0 V

IH

LOW Level Input Voltage 0.8 V

IL

| Magnitude Of Differential Input Voltage 0.1 3.6 V

ID

Common Mode Input Voltage |VID|/2 24-|VID|/2 V

IC

-0.8

V

CC

Operating Temperature Range

A

-40

85

°C

ELECTRICAL CHARACTERISTICS (T
operating conditions unless otherwise noted. All typical values are at T

= -40 to 85°C, and VCC= 3.3V ±10% over recommended

A

=25°C)

A

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

V

|V

∆|V

ITH+

ITH-

Positive-going Differential
Input Voltage Threshold

Negative-going Differential
Input Voltage Threshold

| Differential Output Voltage

OD

Magnitude

| Change in Differential

OD

Output Voltage Magnitude

100 mV

-100 mV

RL= 100Ω VID= ±100mV 247 340 454 mV

-50 50 mV

Between Logic State

∆V

OC(SS)

Change in Steady-state
Common Mode Output

-50 50 mV

Voltage Between Logic
State

V

OC(SS)

V

OC(PP)

I

CC

Steady-state Common
Mode Output Voltage

Peak to Paek Common
mode Output Voltage

Supply Current Enabled, RL= 100Ω 20 30 mA

1.125 1.2 1.375 V

25 150 mV

Disabled 2.5 5 mA

I

Input Current (A or B

I

Inputs)

I

I(OFF)

I

I

I

OC

I

OZ

I

O(OFF)

C

C

Power OFF Input Current VCC= 1.5V VI= 2.4V 3 20 µA
High Level Input Current VIH=2V 7 20 µA

IH

Low Level Input Current VIL= 0.8V 3 10 µA

IL

Short Circuit Output Current V

High Impedance Output
Current

Power OFF Output Current VCC= 1.5V VO= 2.4V ± 1 µA
Input Capacitance (A or B

IN

Inputs)
Output Capacitance (Y or Z

O

Outputs)

VI=0V -2 -11 -20 µA

= 2.4V -1 -3 µA

V

I

or V

O(Y)

=0 ± 3 ± 10 mA

V

OD

=0V ± 6 ± 10 mA

O(Z)

VO= 0 or 2.4V ± 1 µA

VI= 0.4 sin (4e

= 0.4 sin (4e

V

I

6πt

)+0.5V

6πt

)+0.5V, Disabled

3pF

6pF

3/8

STLVDS104

SWITCHING CHA RACTERISTICS (TA= -40 to 85°C, and VCC= 3.3V unless otherwise noted. All typical

values are at T

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

Propagation Delay Time,

PLH

Low to High Output

t

Propagation Delay Time,

PHL

High to Low Output
Differential Output Signal

t

r

Rise Time
Differential Output Signal

t

f

Fall Time

t
t

t

sk(pp)

t

t

Note 1: t
Note2: t

operate with the same supply voltages, at the same temperature, and have identical packages and test circuit.

Pulse Skew (|t

sk(P)

Channel-to-channel Output

sk(O)

Skew (note1)
Part to part Skew (note2) 1.5 ns

Propagation Delay Time,

PZH

High Impedance to High
Level Output

Propagation Delay Time,

t

PZL

High Impedance to Low
Level Output

Propagation Delay Time,

PHZ

High Level to High
Impedance Output

Propagation Delay Time,

t

PLZ

Low Level to High
Impedance Output

sk(O)

sk(pp)

= 25°C)

A

RL= 100Ω CL= 10pF 2.4 3.2 4.2 ns

2.2 3.1 4.2 ns

0.3 0.7 1.2 ns

0.3 0.7 1.2 ns

THL-tTLH

|) 100 300 ps

50 100 ps

7.2 15 ns

8.4 15 ns

3.6 15 ns

615ns

isthetimedifferencebetweenthet
is the magnitudeofthedifference inpropagation delay times between any specified terminals oftwodevices when both devices

PLH

or t

of all drivers of a single device with all their inputs connected together.

PHL

4/8

TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj= 25°C)
Figure 1 : Output Current vs Output High Voltage

Figure 3 : High to Low Propagation Delay Time

STLVDS104

Figure 2 : Output Current vs Output Low Voltage

Figure 4 : Low to High Propagation Delay Time

5/8

STLVDS104

SO-16 MECHANICAL DATA

DIM.

A 1.75 0.068
a1 0.1 0.2 0.004 0.008
a2 1.65 0.064

b 0.35 0.46 0.013 0.018

b1 0.19 0.25 0.007 0.010

C 0.5 0.019
c1 45˚ (typ.)

D 9.8 10 0.385 0.393

E 5.8 6.2 0.228 0.244

e 1.27 0.050

e3 8.89 0.350

F 3.8 4.0 0. 149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1. 27 0.019 0.050
M 0.62 0.024
S8 ˚ (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

6/8

PO13H

STLVDS104

TSSOP16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0079

D 4.9 5 5.1 0.193 0.197 0.201

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0˚ 8˚0˚ 8˚

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

c

K

L

E

D

E1

PIN 1 IDENTIFICATION

1

0080338D

7/8

STLVDS104

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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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