Page 1
N-channel 30 V, 0.0055 Ω, 19 A PowerFLAT™ (5x6)
Features
R
Type V
STL75N3LLZH5 30 V <0.0061 Ω 19 A
1. The value is rated according R
■ R
■ Extremely low on-resistance R
■
Very low switching gate charge
■ High avalanche ruggedness
■ Low gate drive power losses
■ Built in G-S Zener diodes
* Qg industry benchmark
DS(on)
DSS
DS(on)
max
thj-pcb
DS(on)
STL75N3LLZH5
STripFET™ V Power MOSFET
Preliminary data
I
D
(1)
PowerFLAT™ ( 5x6 )
Application
■ Switching applications
Figure 1. Internal schematic diagram
Description
The STL75N3LLZH5 is an N-channel
STripFET™V Power MOSFET which has been
designed to achieve very low on-state resistance
providing also one of the best-in-class figure of
merit (FOM).
Table 1. Device summary
Order code Marking Package Packaging
STL75N3LLZH5 75N3LLZH5 PowerFLAT™ (5x6) Tape and reel
July 2010 Doc ID 17661 Rev 2 1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
9
Page 2
Electrical ratings STL75N3LLZH5
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
P
P
V
V
I
I
D
I
I
D
I
DM
TOT
TOT
DS
GS
(1)
D
(2)
D
Drain-source voltage (VGS = 0) 30 V
Gate-source voltage ± 18 V
Drain current (continuous) at TC = 25 °C 75 A
(1)
Drain current (continuous) at TC = 100 °C 47 A
Drain current (continuous) at TC = 25 °C 19 A
(2)
Drain current (continuous) at TC=100°C 11.8 A
(3)
Drain current (pulsed) 76 A
(1)
Total dissipation at TC = 25°C 60 W
(2)
Total dissipation at TC = 25°C 4 W
Derating factor 0.03 W/°C
T
T
stg
1. The value is rated according R
2. The value is rated according R
3. Pulse width limited by safe operating area.
Operating junction temperature
J
Storage temperature
.
thj-c
thj-pcb.
-55 to 150 °C
Table 3. Thermal resistance
Symbol Parameter Value Unit
R
thj-case
R
thj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Thermal resistance junction-case (Drain) (steady
state)
(1)
Thermal resistance junction-ambient 31.3 °C/W
2/9 Doc ID 17661 Rev 2
2.08 °C/W
Page 3
STL75N3LLZH5 Electrical characteristics
2 Electrical characteristics
(T
= 25 °C unless otherwise specified).
CASE
Table 4. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown
voltage
Zero gate voltage drain
current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
= 250 µA, VGS= 0 30 V
I
D
= max rating,
V
DS
= max rating @125 °C
V
DS
V
= ± 18 V ±10 µA
GS
1
10
Gate threshold voltage VDS= VGS, ID = 250 µA 1 V
Static drain-source on
resistance
= 10 V, ID= 9.5 A
V
GS
= 4.5 V, ID= 9.5 A
V
GS
0.0055
0.0066
0.0061
0.0078ΩΩ
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
C
C
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
V
=25 V, f=1 MHz,
DS
=0
V
GS
1510
-
287
-
40
µA
µA
pF
pF
pF
Q
Q
Q
Total gate charge
g
Gate-source charge
gs
Gate-drain charge
gd
VDD=15 V, ID = 19 A
V
=4.5 V
GS
Figure 3
11.8
-
4
-
6
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off delay time
t
Fall time
f
=15 V, ID= 9.5 A,
V
DD
=4.7 Ω, VGS=10 V
R
G
Figure 2
9.2
11
55
-
20
nC
nC
nC
ns
ns
ns
ns
Doc ID 17661 Rev 2 3/9
Page 4
Electrical characteristics STL75N3LLZH5
Table 7. Source drain diode
Symbol Parameter Test conditions Min Typ. Max Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration= 300 µs, duty cycle 1.5%.
Source-drain current - 19 A
(1)
Source-drain current (pulsed) - 76 A
(2)
Forward on voltage I
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
= 19 A, VGS=0 - 1.1 V
SD
I
= 19 A,
SD
di/dt = 100 A/µs,
=25 V, Tj=150 °C
V
DD
24
-
17
1.4
ns
nC
A
4/9 Doc ID 17661 Rev 2
Page 5
STL75N3LLZH5 Test circuits
3 Test circuits
Figure 2. Switching times test circuit for
PW
resistive load
VD
VGS
RG
RL
D.U.T.
2200
µF
3.3
µF
AM01468v1
V
DD
Figure 4. Test circuit for inductive load
G
25
Ω
switching and diode recovery times
A
D
D.U. T.
S
B
R
FAST
DIODE
G
A
A
L=100µH
B
B
D
G
S
3.3
µF
1000
µF
V
DD
Figure 3. Gate charge test circuit
V
i=20V=VGMAX
PW
2200
µF
1kΩ
12V
IG=CONST
2.7kΩ
47kΩ
47kΩ
100Ω
100nF
D.U.T.
AM01469v1
Figure 5. Unclamped inductive load test
circuit
L
VD
ID
Vi
D.U. T.
2200
µF
3.3
µF
1kΩ
V
VDD
G
VDD
Pw
AM01470v1
Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform
V(BR)DSS
VD
IDM
ID
VDD
VDD
AM01472v1
0
0
10%
tdon
ton
90%
toff
tr
10%
tdoff
VDS
90%
V
GS
Doc ID 17661 Rev 2 5/9
AM01471v1
tf
90%
10%
AM01473v1
Page 6
Package mechanical data STL75N3LLZH5
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK
6/9 Doc ID 17661 Rev 2
Page 7
STL75N3LLZH5 Package mechanical data
Table 8. Power FLAT™ (5x6) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.83 0.93 0.031 0.32 0.036
A1 0.02 0.05 0.0007 0.0019
A3 0.20 0.007
b 0.35 0.40 0.47 0.013 0.015 0.018
D5.00 0.196
D1 4.75 0.187
D2 4.15 4.20 4.25 0.163 0.165 0.167
E6.00 0.236
E1 5.75 0.226
E2 3.43 3.48 3.53 0.135 0.137 0.139
E4 2.58 2.63 2.68 0.103 0.105
e1.27 0.050
L 0.70 0.80 0.90 0.027 0.031 0.035
Figure 8. Power FLAT™ (5x6) drawing
Doc ID 17661 Rev 2 7/9
Page 8
Revision history STL75N3LLZH5
5 Revision history
Table 9. Document revision history
Date Revision Changes
22-Jun-2010 1 First release.
08-Jul-2010 2
Modified V
GS
On/off states
in Table 2: Absolute maximum ratings and Table 4:
.
8/9 Doc ID 17661 Rev 2
Page 9
STL75N3LLZH5
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Doc ID 17661 Rev 2 9/9
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