Page 1
N-channel 40 V, 0.0055 Ω, 18 A, PowerFLAT™ (6x5)
Features
R
Type V
STL70N4LLF5 40 V 0.0065 Ω 18 A
1. The value is rated according R
■ R
■ Extremely low on-resistance R
■
High avalanche ruggedness
■ Low gate drive power losses
* Qg industry benchmark
DS(on)
DSS
Application
■ Switching applications
Description
This product utilizes the 5
rules of ST’s proprietary STripFET™ technology.
The lowest available R
package, makes this device suitable for the most
demanding DC-DC converter applications, where
high power density is to be achieved.
th
DS(on)*Qg
DS(on)
max
thj-pcb
DS(on)
I
D
(1)
generation of design
, in this chip scale
STL70N4LLF5
STripFET™ V Power MOSFET
Preliminary Data
PowerFLAT™ ( 6x5 )
Figure 1. Internal schematic diagram
Table 1. Device summary
Order code Marking Package Packaging
STL70N4LLF5 70N4LLF5 PowerFLAT™ (6x5) Tape and reel
December 2008 Rev 1 1/10
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
10
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Contents STL70N4LLF5
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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STL70N4LLF5 Electrical ratings
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
P
P
V
V
I
I
D
I
I
D
I
DM
TOT
TOT
DS
GS
(1)
D
(2)
D
Drain-source voltage (VGS = 0) 40 V
Gate-source voltage ± 22 V
Drain current (continuous) at TC = 25 °C 70 A
(1)
Drain current (continuous) at TC = 100 °C 44 A
Drain current (continuous) at TC = 25 °C 18 A
(3)
Drain current (continuous) at TC=100 °C 11.5 A
(3)
Drain current (pulsed) 72 A
(1)
Total dissipation at TC = 25 °C 60 W
(2)
Total dissipation at TC = 25 °C 4 W
Derating factor 0.03 W/°C
T
T
stg
1. The value is rated according R
2. The value is rated according R
3. Pulse width limited by safe operating area
Operating junction temperature
J
Storage temperature
thj-c
thj-pcb
-55 to 150 °C
Table 3. Thermal resistance
Symbol Parameter Value Unit
R
thj-case
R
thj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Thermal resistance junction-case (drain) (steady state) 2.08 °C/W
(1)
Thermal resistance junction-ambient 31.3 °C/W
Table 4. Avalanche data
Symbol Parameter Value Unit
I
AV
E
AS
Not-repetitive avalanche current,
(pulse width limited by Tj Max)
Single pulse avalanche energy
(starting TJ = 25 °C, ID = I
AV
, V
DD
= 24 V)
TBD A
TBD mJ
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Page 4
Electrical characteristics STL70N4LLF5
2 Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 5. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown
voltage
Zero gate voltage drain
current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
Gate threshold voltage
Static drain-source on
resistance
= 250 µA, VGS= 0
I
D
V
= Max rating,
DS
V
= Max rating @125 °C
DS
= ±22 V
V
GS
= VGS, ID = 250 µA
V
DS
= 10 V, ID= 9 A
V
GS
= 4.5 V, ID= 9 A
V
GS
40 V
1
10
±100 nA
1V
0.0055
TBD
0.0065
0.009ΩΩ
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
C
C
Q
Q
Q
R
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
g
Total gate charge
Gate-source charge
gs
Gate-drain charge
gd
Gate input resistance
G
= 25 V, f=1 MHz,
V
DS
=0
V
GS
=15 V, ID = 18 A
V
DD
= 4.5 V
V
GS
(see Figure 3)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
1800
270
40
13
TBD
TBD
TBD Ω
µA
µA
pF
pF
pF
nC
nC
nC
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STL70N4LLF5 Electrical characteristics
Table 7. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off delay time
Fall time
t
f
=15 V, ID= 9A,
V
DD
=4.7 Ω, VGS=10 V
R
G
(see Figure 2)
TBD
TBD
TBD
TBD
ns
ns
ns
ns
Table 8. Source drain diode
Symbol Parameter Test conditions Min Typ. Max Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Source-drain current 18 A
(1)
Source-drain current (pulsed) 72 A
(2)
Forward on voltage
rr
Reverse recovery time
Reverse recovery charge
rr
Reverse recovery current
= 18A, VGS=0
I
SD
= 18A,
I
SD
di/dt = 100 A/µs,
= 25 V
V
DD
TBD
TBD
TBD
1.1 V
ns
nC
A
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Page 6
Test circuits STL70N4LLF5
3 Test circuits
Figure 2. Switching times test circuit for
resistive load
Figure 4. Test circuit for inductive load
switching and diode recovery times
Figure 3. Gate charge test circuit
Figure 5. Unclamped inductive load test
circuit
Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform
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Page 7
STL70N4LLF5 Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
7/10
Page 8
Package mechanical data STL70N4LLF5
PowerFLAT™(6x5) mechanical data
DIM.
A 0.80 0.83 0.93 0.031 0.32 0.036
A1 0.02 0.05 0.0007 0.0019
A3 0.20 0.007
b 0.35 0.40 0.47 0.013 0.015 0.018
D 5.00 0.196
D1 4.75 0.187
D2 4.15 4.20 4.25 0.163 0.165 0.167
E 6.00 0.236
E1 5.75 0.226
E2 3.43 3.48 3.53 0.135 0.137 0.139
E4 2.58 2.63 2.68 0.103 0.105
e 1.27 0.050
L 0.70 0.80 0.90 0.027 0.031 0.035
Min. Typ. Max. Min. Typ. Max.
mm. inch
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Page 9
STL70N4LLF5 Revision history
5 Revision history
Table 9. Document revision history
Date Revision Changes
01-Dec-2008 1 First release
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Page 10
STL70N4LLF5
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