Page 1
STL40DN3LLH5
Dual N-channel 30 V, 0.016 Ω, 11 A
PowerFLAT™ (5x6) double island, STripFET™ V Power MOSFET
Preliminary data
Features
Type V
STL40DN3LLH5 30 V < 0.018 Ω 11 A
DSS
R
DSo(n)
I
D
(1)
1. The value is rated according R
■ R
■ Extremely low on-resistance R
■
Very low switching gate charge
■ High avalanche ruggedness
■ Low gate drive power losses
* Qg industry benchmark
DS(on)
thj-pcb
DS(on)
Application
Switching applications
Description
This product utilizes the 5
rules of ST’s proprietary STripFET™ technology.
The lowest available R
package, makes this device suitable for the most
demanding DC-DC converter applications, where
high power density is to be achieved.
th
generation of design
DS(on)*Qg
, in this chip scale
PowerFLAT™ (5x6)
Double island
Figure 1. Internal schematic diagram
Table 1. Device summary
Order code Marking Package Packaging
STL40DN3LLH5 40DN3LLH5
January 2011 Doc ID 18416 Rev 1 1/11
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
PowerFLAT™(5x6)
Double island
Tape and reel
www.st.com
11
Page 2
Contents STL40DN3LLH5
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2/11 Doc ID 18416 Rev 1
Page 3
STL40DN3LLH5 Electrical ratings
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
P
P
V
V
I
D
I
D
I
D
I
D
I
DM
TOT
TOT
DS
GS
(1)
(2)
Drain-source voltage (VGS = 0) 30 V
Gate-source voltage ± 22 V
Drain current (continuous) at TC = 25 °C 40 A
(1)
Drain current (continuous) at TC = 100 °C 26 A
Drain current (continuous) at TC = 25 °C 11 A
(2)
Drain current (continuous) at TC=100°C 7 A
(3)
Drain current (pulsed) 44 A
(1)
Total dissipation at TC = 25°C 60 W
(2)
Total dissipation at TC = 25°C 4 W
Derating factor 0.03 W/°C
T
T
stg
1. The value is rated according R
2. The value is rated according R
3. Pulse width limited by safe operating area
Operating junction temperature
J
Storage temperature
thj-c
thj-pcb
-55 to 150 °C
Table 3. Thermal resistance
Symbol Parameter Value Unit
R
thj-case
R
thj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Thermal resistance junction-case (drain) (steady state) 2.08 °C/W
(1)
Thermal resistance junction-ambient 32 °C/W
Doc ID 18416 Rev 1 3/11
Page 4
Electrical characteristics STL40DN3LLH5
2 Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 4. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown
voltage
Zero gate voltage drain
current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
Gate threshold voltage
Static drain-source on
resistance
= 250 µA, VGS= 0
I
D
V
= Max rating,
DS
V
= Max rating @125 °C
DS
= ± 22 V
V
GS
= VGS, ID = 250 µA
V
DS
= 10 V, ID= 5.5 A
V
GS
= 4.5 V, ID= 5.5 A
V
GS
30 V
1
10
±100 nA
11.5 V
0.016
0.02
0.018
0.025ΩΩ
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
C
C
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
V
=25 V, f=1 MHz, VGS=0
DS
475
-
97
-
19
µA
µA
pF
pF
pF
Q
g
Total gate charge
Q
Q
Gate-source charge
gs
Gate-drain charge
gd
=15 V, ID = 11 A
V
DD
V
=4.5 V
GS
(see Figure 3)
4/11 Doc ID 18416 Rev 1
4.5
-
1.7
1.9
nC
-
nC
nC
Page 5
STL40DN3LLH5 Electrical characteristics
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off delay time
Fall time
t
f
=15 V, ID= 11 A,
V
DD
=4.7 Ω, VGS=10 V
R
G
(see Figure 2)
-
4
22
13
2.8
ns
ns
ns
ns
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Source-drain current - 11 A
(1)
Source-drain current (pulsed) - 44 A
(2)
Forward on voltage
rr
Reverse recovery time
Reverse recovery charge
rr
Reverse recovery current
= 11 A, VGS=0
I
SD
= 11 A,
I
SD
di/dt = 100 A/µs,
V
=25 V, Tj=150 °C
DD
-1.1V
16.2
-
1
8.1
ns
nC
A
Doc ID 18416 Rev 1 5/11
Page 6
Test circuits STL40DN3LLH5
3 Test circuits
Figure 2. Switching times test circuit for
PW
resistive load
VD
VGS
RG
RL
D.U.T.
2200
μF
3.3
μF
AM01468v1
V
DD
Figure 4. Test circuit for inductive load
G
25
Ω
switching and diode recovery times
A
D
D.U. T.
S
B
R
FAST
DIODE
G
A
A
L=100μH
B
B
D
G
S
3.3
μF
1000
μF
V
DD
Figure 3. Gate charge test circuit
V
i=20V=VGMAX
PW
2200
μF
1kΩ
12V
IG=CONST
2.7kΩ
47kΩ
47kΩ
100Ω
100nF
D.U.T.
AM01469v1
Figure 5. Unclamped inductive load test
circuit
L
VD
ID
Vi
D.U. T.
2200
μF
3.3
μF
1kΩ
VDD
V
VDD
G
Pw
AM01470v1
Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform
V(BR)DSS
VD
IDM
ID
VDD
VDD
AM01472v1
0
0
10%
tdon
ton
90%
tr
10%
tdoff
VDS
90%
V
GS
6/11 Doc ID 18416 Rev 1
AM01471v1
toff
tf
90%
10%
AM01473v1
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STL40DN3LLH5 Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
Doc ID 18416 Rev 1 7/11
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Package mechanical data STL40DN3LLH5
Table 8. PowerFLAT™ (5x6) double island mechanical data
mm
Dim.
Min. Typ. Max.
A 0.80 0.83 0.90
A1 0.02 0.05
A3 0.20
b 0.35 0.40 0.47
D5.00
D1 4.75
D2 4.11 4.21 4.31
E6.00
E1 5.75
E2 3.51 3.61 3.71
E3 2.32 2.42 2.52
e1.27
L 0.70 0.80 0.90
L1 0.48 0.58 0.68
8/11 Doc ID 18416 Rev 1
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STL40DN3LLH5 Package mechanical data
Figure 8. PowerFLAT™ (5x6) double island drawing
Doc ID 18416 Rev 1 9/11
Page 10
Revision history STL40DN3LLH5
5 Revision history
Table 9. Document revision history
Date Revision Changes
24-Jan-2011 1 First release
10/11 Doc ID 18416 Rev 1
Page 11
STL40DN3LLH5
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Doc ID 18416 Rev 1 11/11
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