Datasheet stl23nm60nd Datasheet

STL23NM60ND

N-channel 600 V, 0.150 Ω, 19.5 A, FDmesh™ II Power MOSFET

(with fast diode) PowerFLAT™ (8x8) HV

Preliminary data

Features

V

Type

(@T

DSS

jmax

)

R

DS(on)

max I

STL23NM60ND 650 V < 0.180 Ω 19.5 A

1. This value is rated according to R

■ The worldwide best R

thj-case.

* area amongst the

DS(on)

fast recovery diode devices

■ 100% avalanche tested

■ Low input capacitance and gate charge

■ Low gate input resistance

■ High dv/dt and avalanche capabilities

D

(1)

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Application

■ Switching applications

Description

The FDmesh™ II series belongs to the second
generation of MDmesh™ technology. This
revolutionary Power MOSFET associates a new
vertical structure to the company's strip layout
and associates all advantages of reduced on­resistance and fast switching with an intrinsic fast­recovery body diode.It is therefore strongly
recommended for bridge topologies, in particular
ZVS phase-shift converters.

Table 1. Device summary

Order code Marking Package Packaging

STL23NM60ND 23NM60ND PowerFLAT™ 8x8 HV Tape and reel

Figure 1. Internal schematic diagram

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April 2010 Doc ID 17439 Rev 1 1/11

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

www.st.com

11

Contents STL23NM60ND

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2/11 Doc ID 17439 Rev 1

STL23NM60ND Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

V

I

D

I

D

I

DM

I

D

I

D

I

DM

P

TOT

P

TOT

I

E

dv/dt

T

1. The value is rated according to R

2. Pulse width limited by safe operating area

3. When mounted on FR-4 board of inch², 2oz Cu

4. ISD ≤ 19.5 A, di/dt ≤ 400 A/µs, V

Drain-source voltage (VGS = 0) 600 V

DS

Gate-source voltage ± 25 V

GS

(1)

Drain current (continuous) at TC = 25 °C 19.5 A

(1)

Drain current (continuous) at TC = 100 °C 11.7 A

(1),(2)

Drain current (pulsed) 78 A

(3)

Drain current (continuous) at TC = 25 °C 2.75 A

(3)

Drain current (continuous) at TC = 100 °C 1.75 A

(2),(3)

Drain current (pulsed) 11 A

(3)

Total dissipation at TC = 25 °C (steady state) 150 W

(1)

Total dissipation at TC = 25 °C (steady state) 3 W

Avalanche current, repetitive or not-

AR

repetitive (pulse width limited by Tj max)

Single pulse avalanche energy

AS

(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

(4)

Peak diode recovery voltage slope 40 V/ns

Storage temperature - 55 to 150 °C

stg

Max. operating junction temperature 150 °C

T

j

thj-case

< V

Peak

(BR)DSS

9A

700 mJ

Table 3. Thermal data

Symbol Parameter Value Unit

R

thj-case

R

thj-amb

1. When mounted on 1inch² FR-4 board, 2 oz Cu

Thermal resistance junction-case max 0.83 °C/W

(1)

Thermal resistance junction-amb max 45 °C/W

Maximum lead temperature for soldering

T

l

purposes

300 °C

Doc ID 17439 Rev 1 3/11

Electrical characteristics STL23NM60ND

2 Electrical characteristics

(T

= 25 °C unless otherwise specified)

CASE

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

dv/dt

I

DSS

I

GSS

V

GS(th)

R

DS(on)

1. Characteristic value at turn off on inductive load

Drain-source breakdown
voltage

(1)

Drain-source voltage slope

Zero gate voltage drain
current (VGS = 0)

Gate body leakage current

= 0)

(V

DS

= 1 mA, VGS= 0 600 V

I

D

V

= 480 V, ID = 19.5 A,

DD

= 10 V

V

GS

= Max rating,

V

DS

= Max rating,@125 °C

V

DS

V

= ±20 V 100 nA

GS

48 V/ns

Gate threshold voltage VDS= VGS, ID = 250 µA 3 4 5 V

Static drain-source on
resistance

V

= 10 V, ID= 10 A 0.150 0.180 Ω

GS

1

100µAµA

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Input capacitance

iss

Output capacitance

oss

Reverse transfer

rss

capacitance

Equivalent output

(1)

capacitance

C

oss eq.

C

C

C

Rg Gate input resistance

Q

Q

Q

1. C
increases from 0 to 80% V

Total gate charge

g

Gate-source charge

gs

Gate-drain charge

gd

is defined as a constant equivalent capacitance giving the same charging time as C

oss eq.

DSS

= 50 V, f =1 MHz,

V

DS

= 0

V

GS

V

GS

= 0, V

= 0 to 480 V - 318 - pF

DS

f=1 MHz Gate DC Bias=0
Test signal level=20 mV
open drain

= 480 V, ID = 19.5 A

V

DD

= 10 V

V

GS

(see Figure 3)

2050

-

80

8

pF

-

pF
pF

-4-Ω

70

-

10
30

when VDS

oss

nC

-

nC
nC

4/11 Doc ID 17439 Rev 1

STL23NM60ND Electrical characteristics

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

t

d(off)

Turn-on delay time
Rise time

r

Turn-off delay time

t

Fall time

f

= 300 V, ID = 10 A,

V

DD

= 4.7 Ω, VGS = 10 V

R

G

(see Figure 2)

25
45

­90

-

40

Table 7. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

I

SDM

V

SD

Q

I

RRM

Q

I

RRM

1. Pulse width limited by safe operating area.

2. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Source-drain current

SD

(1)

Source-drain current (pulsed)

(2)

Forward on voltage ISD = 19.5 A, VGS=0 - 1.3 V

t

Reverse recovery time

rr

Reverse recovery charge

rr

Reverse recovery current

Reverse recovery time

t

rr

Reverse recovery charge

rr

Reverse recovery current

= 19.5 A, di/dt =100 A/µs,

I

SD

= 100 V

V

DD

(see Figure 4)

= 100 V

V

DD

di/dt =100 A/µs, I

= 19.5 A,

SD

Tj = 150 °C
(see Figure 4)

-

-

-

19.578A

190

1.2
13

260

2.0
15

ns
ns
ns
ns

A

ns

µC

A

ns

µC

A

Doc ID 17439 Rev 1 5/11

Test circuits STL23NM60ND

3 Test circuits

Figure 2. Switching times test circuit for

PW

resistive load

VGS

VD

RG

RL

D.U.T.

2200

µF

3.3
µF

AM01468v1

V

DD

Figure 4. Test circuit for inductive load

G

25

Ω

switching and diode recovery times

A

D

D.U. T.

S

B

R

FAST
DIODE

G

A

A

L=100µH

B

B

D

G

S

3.3

µF

1000

µF

V

DD

Figure 3. Gate charge test circuit

V

i=20V=VGMAX

PW

2200
µF

1kΩ

12V

IG=CONST

2.7kΩ

47kΩ

47kΩ

100Ω

1kΩ

100nF

D.U.T.

AM01469v1

Figure 5. Unclamped inductive load test

circuit

L

VD

ID

Vi

D.U. T.

2200

µF

3.3
µF

VDD

V

VDD

G

Pw

AM01470v1

Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform

V(BR)DSS

VD

IDM

VDD

ID

VDD

AM01472v1

0

0

6/11 Doc ID 17439 Rev 1

10%

tdon

ton

90%

toff

tr

10%

tdoff

VDS

90%

V

GS

AM01471v1

tf

90%

10%

AM01473v1

STL23NM60ND Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK®

Doc ID 17439 Rev 1 7/11

Package mechanical data STL23NM60ND

Table 8. PowerFLAT™ 8x8 HV mechanical data

mm

Dim.

Min. Typ. Max.

A 0.80 0.90 1.00

A1 0.02 0.05

b 0.95 1.00 1.05

c0.10

D8.00

E8.00

D2 7.05 7.20 7.30

E2 4.15 4.30 4.40

e2.00

L 0.40 0.50 0.60

Figure 8. PowerFLAT™ 8x8 HV drawing mechanical data

e

L

PIN#1 ID

0.40

D2

b

BOTTOM VIEW

E2

D

INDEX AREA

TOP VIEW

E

SIDE VIEW

A

0.08 C

8/11 Doc ID 17439 Rev 1

A1

SEATING

PLANE

AM05542v1

STL23NM60ND Package mechanical data

Figure 9. PowerFLAT™ 8x8 HV recommended footprint

7.30

4.40

2.00

1.05

0.60

AM05543v1

Doc ID 17439 Rev 1 9/11

Revision history STL23NM60ND

5 Revision history

Table 9. Document revision history

Date Revision Changes

28-Apr-2010 1 First release

10/11 Doc ID 17439 Rev 1

STL23NM60ND

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Doc ID 17439 Rev 1 11/11