Datasheet stl15dn4f5 Datasheet

STL15DN4F5

Dual N-channel 40 V, 8 mΩ, 15 A

PowerFLAT™(5x6) double island, STripFET™ V Power MOSFET

Features

R

thj-pcb

DS(on)

max.

DS(on)

I

D

(1)

PowerFLAT™ (5x6)

Double island

Figure 1. Internal schematic diagram

Type V

STL15DN4F5 40 V 9 mΩ 15 A

1. The value is rated according R

■ R

■ Extremely low on-resistance R

■

Very low switching gate charge

■ Low gate drive power losses

* Qg industry benchmark

DS(on)

DSS

Application

■ Switching applications

– Automotive

Description

The device is a dual N-channel STripFET™ V. This Power MOSFET technology is among the latest improvements, which have been especially tailored to achieve very low on-state resistance providing also one of the best-in-class figure of merit (FOM).

Table 1. Device summary

Order code Marking Package Packaging

STL15DN4F5 15DN4F5

PowerFLAT™(5x6)

Double island

Tape and reel

September 2010 Doc ID 17739 Rev 1 1/12

www.st.com

12

Contents STL15DN4F5

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/12 Doc ID 17739 Rev 1

STL15DN4F5 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

P

V

I

D

I

DM

TOT

DS

GS

(1)

D

(2)

D

Drain-source voltage (VGS = 0) 40 V

Gate-source voltage ± 20 V

Drain current (continuous) at TC = 25 °C

(silicon limited)

60 A

Drain current (continuous) at TC = 25 °C 15 A

(2)

Drain current (continuous) at TC = 100°C 10 A

(3)

Drain current (pulsed) 60 A

(1)

Total dissipation at TC = 25°C 60 W

(2)

Total dissipation at TC = 25°C, t < 10 sec 4.3 W

Derating factor 0.03 W/°C

T

stg

1. The value is rated according R

2. The value is rated according R

3. Pulse width limited by safe operating area

Operating junction temperature

J

Storage temperature

thj-c

thj-pcb

-55 to 175 °C

Table 3. Thermal resistance

Symbol Parameter Value Unit

R

thj-case

R

thj-pcb

1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec (see Figure 3)

Thermal resistance junction-case (drain) (steady state) 2.5 °C/W

(1)

Thermal resistance junction-ambient 35 °C/W

Table 4. Avalanche data

Symbol Parameter Value Unit

I

AV

E

AS

1. Tested at wafer level only.

Not-repetitive avalanche current, (pulse width limited by Tj max.)

Single pulse avalanche energy

(1)

(starting T

= 25 °C, ID = I

J

7.5 A

AV

, V

DD

= 24 V)

150 mJ

Doc ID 17739 Rev 1 3/12

Electrical characteristics STL15DN4F5

2 Electrical characteristics

(T

= 25 °C unless otherwise specified)

CASE

Table 5. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Drain-source breakdown voltage

Zero gate voltage drain current (VGS = 0)

Gate body leakage current

= 0)

(V

DS

Gate threshold voltage

Static drain-source on resistance

= 250 µA, VGS= 0

I

D

V

= Max rating,

DS

V

= Max rating @125 °C

DS

= ±20 V

V

GS

= VGS, ID = 250 µA

V

DS

VGS= 10 V, ID= 7.5 A

40 V

1

10

±100 nA

24V

89mΩ

Table 6. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

C

Q

Input capacitance

iss

Output capacitance

oss

Reverse transfer

rss

capacitance

g

Total gate charge Gate-source charge

gs

Gate-drain charge

gd

= 25 V, f = 1 MHz

V

DS

= 0

V

GS

= 20 V, ID = 15 A

V

DD

= 10 V

V

GS

(see Figure 14)

1550

-

230

-

25

-

6

-

5.5

µA µA

pF pF pF

nC nC nC

4/12 Doc ID 17739 Rev 1

STL15DN4F5 Electrical characteristics

Table 7. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

Turn-on delay time

t

Rise time

r

Turn-off delay time

Fall time

t

f

V

= 20 V, ID = 7.5 A,

DD

= 4.7 Ω, V

R

G

(see Figure 13)

GS

= 10 V

18 45

32

-

5

Table 8. Source drain diode

Symbol Parameter Test conditions Min Typ. Max Unit

I

SD

I

SDM

V

SD

t

Q

I

RRM

1. Pulse width limited by safe operating area

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %

Source-drain current - 15 A

(1)

Source-drain current (pulsed) - 60 A

(2)

Forward on voltage I

rr

Reverse recovery time Reverse recovery charge

rr

Reverse recovery current

= 15 A, V

I

SD

= 15 A,

GS

di/dt = 100 A/µs,

= 32 V, Tj = 150 °C

V

DD

= 0 - 1.1 V

30

-

35

2.2

ns ns ns ns

ns

nC

A

Doc ID 17739 Rev 1 5/12

Electrical characteristics STL15DN4F5

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance

I

(A)

100

D

Operation in this area is

Limited by max R

DS(on)

Tj=175°C Tc=25°C Single pulse

10

AM07129v1

10ms

1

100ms

1s

0.1

0.01

0.1

Figure 4. Output characteristics Figure 5. Transfer characteristics

I

D

(A)

1

VGS=10V

35

30

25

20

15

10

5

0

Figure 6. Normalized B

BV

DSS

(norm)

0.2

0

0.4

1.15

10

V

DS

(V)

AM07130v1

I

(A)

D

V

DS

=0.4V

35

6V

5V

30

25

20

15

10

5

4V

0.8

V

DS

0.6

vs temperature Figure 7. Static drain-source on resistance

VDSS

(V)

AM07132v1

R

DS(on)

(mOhm)

0

2

4

6

VGS=10V

8.6

1.10

AM07131v1

8

V

GS

(V)

AM07133v1

1.05

1.00

0.95

0.90

0.85

0.80

-50

-75

-25

25

75

50

0

100

125

150

T

J

(°C)

6/12 Doc ID 17739 Rev 1

8.2

7.8

7.4

7.0 468 10

2

0

12

14

D

(A)

I

STL15DN4F5 Electrical characteristics

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations

V

GS

(V)

VDD=20V

I

D

=15A

10

8

6

4

AM07135v1

(pF)

1000

100

C

AM07134v1

Ciss

Coss

2

0

10

5

15

20

25

Q

g

(nC)

Figure 10. Normalized gate threshold voltage

V

(norm)

vs temperature

GS(th)

1.00

0.8

0.6

0.4

-75

-50

-25

AM07136v1

25

0

50

75

100

125

150

T

J

(°C)

Figure 12. Source-drain diode forward

characteristics

V

SD

(V)

TJ=-55°C

0.9

AM07138v1

10

0.1

1

10

V

Figure 11. Normalized on resistance vs

temperature

R

DS(on)

(norm)

2.0

1.5

1.0

0.5

0

-50

-75

-25

25

0

50

75

100

125 150

Crss

DS

(V)

AM07137v1

T

J

(°C)

0.8

0.7

0.6

0.5

0.4 0

TJ=25°C

2

TJ=175°C

6

4

8

10

12

14

I

SD

(A)

Doc ID 17739 Rev 1 7/12

Test circuits STL15DN4F5

3 Test circuits

Figure 13. Switching times test circuit for

PW

resistive load

VD

VGS

RG

RL

D.U.T.

2200

µF

3.3 µF

AM01468v1

V

DD

Figure 15. Test circuit for inductive load

G

25

Ω

switching and diode recovery times

A

D

D.U. T.

S

B

R

FAST DIODE

G

A

L=100µH

B

D

G

S

3.3

µF

1000 µF

V

DD

Figure 14. Gate charge test circuit

V

i=20V=VGMAX

PW

2200 µF

1kΩ

12V

IG=CONST

2.7kΩ

47kΩ

100Ω

100nF

D.U.T.

AM01469v1

Figure 16. Unclamped inductive load test

circuit

L

VD

ID

Vi

D.U. T.

2200

µF

3.3 µF

1kΩ

VDD

V

VDD

G

Pw

AM01470v1

Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

V(BR)DSS

VD

IDM

ID

VDD

AM01472v1

0

10%

tdon

ton

90%

tr

10%

tdoff

VDS

90%

V

GS

8/12 Doc ID 17739 Rev 1

AM01471v1

toff

tf

90%

10%

AM01473v1

STL15DN4F5 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and products status are available at: www.st.com ECOPACK is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK®

.

Doc ID 17739 Rev 1 9/12

Package mechanical data STL15DN4F5

PowerFLAT™ (5x6) double island mechanical data

Dim

Min Typ Max

A0.800.83 0.90

A1 0.02 0.05

A3 0.20

b 0.35 0.40 0.47

D5.00

D1 4.75

D2 4.11 4.21 4.31

E6.00

E1 5.75

E2 3.51 3.61 3.71

E3 2.32 2.42 2.52

e1.27

L 0.70 0.800.90

L1 0.48 0.58 0.68

mm

8066312_A

10/12 Doc ID 17739 Rev 1

STL15DN4F5 Revision history

5 Revision history

Table 9. Document revision history

Date Revision Changes

02-Sep-2010 1 First release

Doc ID 17739 Rev 1 11/12

STL15DN4F5

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12/12 Doc ID 17739 Rev 1