Datasheet STK55C324 Datasheet (Syntek Semiconductor)

Syntek Semiconductor Co., Ltd.

Specification

1. FEATURES :

* Operating voltage : 2.5V – 5.5 V.
* Maximum CPU operating frequency : 2MHz at 2.7V
* Dual oscillators :

- RC or 32.768 KHz crystal oscillator for LCD display and watch timer.

- RC oscillator for system clock.

* 40 segments and 8 commons output for LCD driver.

- 1/4 bias, 1/8 duty and 64Hz frame frequency.

- 16 levels contrast control.

* I/O port.

STK55C324

- 8 I/O pins with selectable wake up interrupt.

- Two output pins. These two pins can be set as sound channel DAC outputs.
* Built in 160 bytes data RAM and 40 bytes display RAM.
* Built in 32K bytes ROM for program.
* One 8-bit timer with 8 predefined input clock.
* Two sound generators with 7-bit D/A output.
* Four interrupt sources :

NMI - 64 Hz interrupt
IRQ1 - Fix-time timer interrupt
IRQ2 - Timer interrupt
IRQ3 - External interrupt

* Code option :

- Built-in 150K OHM pull-up resistors for I/O port.

- RC or 32768Hz crystal oscillation for LCD driver.

2. APPLICATION :

* Calculator
* Hand-held game
* Small instrument
* Toy

LCD Controller 1 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

control

32768Hz

C0-C7

S0-S39

3. BLOCK DIAGRAM :

OSC1 OSC2

STK55C324

RC oscillator

ROM

32Kx8

RAM

160x8

LCD RAM

40x8

Address

8-bit CPU

A0-A15 IRQ

Clock

Generator

CONTRAST

LCD driver with

4-bit contrast

8-bit Timer

decoder

D0-D7

Two sound generator

Port 1

P10-P17 SOUND1 SOUND2

LCD Controller 2 /24 Issue date: 13 August, 1999

with 7-bit D/A

Syntek Semiconductor Co., Ltd.

4. PIN DESCRIPTION : (Total 66 pads)

Pin name I/O Function description
COM0-COM7 O LCD common output pins
SEG0-SEG39 O LCD segment output pins
P10-P17 I/O 8-bit I/O pins for port 1
OSC1 I Main system oscillator input pin for chip
OSC2 O Main system oscillator output pin for resistor
XOSC1 I 32.768K Hz crystal oscillator input
XOSC2 O 32.768K Hz crystal oscillator output
SOUND1 O Sound channel 1 output with volume control. This pin is

CMOS output when sound channel is disabled.

STK55C324

SOUND2 O Sound channel 2 output with volume control. This pin is

CMOS output when sound channel is disabled.
/RES I System reset pin with 150K pull-up resistor.
CONTRAST I Bias voltage input pin. Add a resistor to Vdd can

change the LCD contrast.
VDD Power input
VSS Signal ground

5. ADDRESS ARRANGEMENT

1) RAM
0000-003C for LCD output data storage. The memory address which are not specified in the table are

not implemented

Memory address Pin for 1/8 duty
0000-0004 COM0
0008-000C COM1
0010-0014 COM2
0018-001C COM3
0020-0024 COM4
0028-002C COM5
0030-0034 COM6
0038-003C COM7

The LSB of low byte – SEG0.

The MSB of high byte – SEG39.

LCD Controller 3 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

The middle bits are in the order.

0040-00DF for zero page area.
0100-01DF for stacks. This area is overlapped with 0000-00DF.

2) ROM

8000-FFFF for program area.

FFFF, FFFE - IRQ vector.
FFFD, FFFC - RES vector.
FFFB, FFFA - NMI vector.

3) Others

STK55C324

1000 To enter stand-by mode. Write only.

* Write this address, the CPU will be hold with LCD state no change.
* When in stand-by mode, the NMI and IRQ will wake up the CPU.

1001 To enter sleep mode. Write only.

Bit 0 = 1 Sleep mode 1

1 = 1 Sleep mode 2
In sleep mode 1, both of the main system oscillator and 32.768KHz sub-system oscillator will be
stopped. So, all functions are stopped and only external interrupt can wake up this chip. The LCD
display will be turn off while getting into sleep mode 1. If the LCD is turned on after wake-up
immediately, then some garbage may display on the LCD. It is better to turn off the LCD by software
before enter sleep mode 1. After wake up, the software has to delay several ms before turn on the
LCD because the crystal will take several mS to stable.
In sleep mode 2, only main system oscillator will be stopped. So, the following functions will still keep
working.

* The LCD will be kept on.

* The fix-time timer will keep going.

* The NMI, port 1, and fix-time timer interrupt will wake up this chip.

* CPU will keep working if clock source is 32.768K Hz.

1002 Watch timer control register. Write only.

Bit 1 : = 0 Set fix-time timer interrupt at 2 Hz

= 1 Set fix-time timer interrupt at 1 Hz

LCD Controller 4 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

4 : = 0 CPU clock is system clock.

= 1 CPU clock is 32.768K Hz.

7-5 : Reserved.

The default values for each bit is zero.

1003 IRQ flag register. Read & write.

Read function :
Bit 0 : = 1 Fix-time timer interrupt, IRQ1.

1 : = 1 Timer interrupt, IRQ2.

2 : = 1 External interrupt, IRQ3.
Write function :
Bit 0 : = 0 Clear fix-time timer interrupt.

1 : = 0 Clear timer interrupt.

STK55C324

2 : = 0 Clear external interrupt.

* Before firmware exits the interrupt routine, the interrupt flag must be cleared. Otherwise, the IC will

get into interrupt again.

* Write 0 to clear the corresponding IRQ but do not use ‘STZ $1003’ to clear all interrupts at the

same time. Following instructions are recommended

LDA $1003
STA IRQBuff
EOR #0FFH
STA $1003 ;Clear all active interrupts at the same time
LDA IRQBuff
AND #1
BEQ next_irq

* Do NOT use TRB to test and clear this register. Following instructions are recommended.

LDA $1003
AND #1 ;Check IRQ 1
BEQ next_irq
STA $1003 ;Clear the active interrupt.

1004 Port 1 data. Read & write.

1005 Set port 1 bit function. Write only.

* An '1' in this register will set the corresponding pin of port 1 as an output pin.
* The default values for each bit is zero. A pull-up resistor can be added to the pin by code option.

LCD Controller 5 /24 Issue date: 13 August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

But the pull-up resistor will be disabled if this pin is set as output.

1008 Volume control for sound channel 1. Write only.

Bit 7-1 : Volume for sound channel 1. $FF is the maximum volume. If bit 1 of $1013 is zero, then bit

1 will output to SOUND 1 pin.

1009 Volume control for sound channel 2. Write only.

Bit 7-1 : Volume for sound channel 2. $FF is the maximum volume. If bit 3 of $1013 is zero, then bit

1 will output to SOUND 2 pin.

100C Set port 1 bit interrupt function. Write only.

* An '1' in this register will set the interrupt function of the corresponding pin of port 1 to be enable.

That is, an interrupt will be generated if a low level is detected in the pin.

* If port 1 are used as key inputs, there are several interrupts will be generated during key pressing

or release. This is caused by key bounce. It is suggested to disable the port1 interrupt after port 1
interrupt is detected and enable the port 1 interrupt after key released. Or enable port 1 interrupt
before entering sleep or standby mode and disable port 1 interrupt after IC wakeup.

* The default values for each bit is zero.

100D Timer 1 data. Read & write.

* Before writing $100D, the program should select timer clock ($100E) first.
* After timer 1 been enabled, the timer will start to count down. When timer counts to zero, the timer

will count from the initial value and IRQ2 will happen.
* Valid values are from 1 to 255. Zero is prohibited.
* If CPU read this register, the value will be 1 to 255. Please note that the CPU will never read a

zero from timer.
* The time elapse = ($100D)/timer clock

100E Timer 1 clock select and contrast setting. Write only.

Bit 2-0 : = 000 System clock/2

= 001 System clock/4
= 010 System clock/8
= 011 System clock/16
= 100 System clock/32
= 101 System clock/64
= 110 System clock/128
= 111 System clock/256

LCD Controller 6 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

3 : Reserved
7-4 : LCD contrast control. The minimum contrast value is zero and the maximum contrast value

is 0FH. The default state is maximum contrast.

The default values of bit 3-0 are unknown.

100F Control register. Write only.

Bit 1 : = 0 Disable timer 1 interrupt.

= 1 Enable timer 1 interrupt.

2 : = 0 Disable NMI.

= 1 Enable NMI.

3 : = 0 Disable timer 1.

= 1 Enable timer 1.

4 : = 0 LCD off.

STK55C324

= 1 LCD on.

6 : = 0 Disable fix-time timer interrupt.

= 1 Enable fix-time timer interrupt.

* The default values for each bit is zero.

1010 Sound generator clock select. Write only.

Bit 2-0 : Sound generator 1 clock select.

6-4 : Sound generator 2 clock select.

= 000 System clock/2
= 001 System clock/4
= 010 System clock/8
= 011 System clock/16
= 100 System clock/32
= 101 System clock/64
= 110 System clock/128
= 111 System clock/256

7&3 : Reserved

The default value is unknown.

1011 Sound generator 1 data. Write only.

* Before writing $1011, the program should select timer clock ($1010) first.
* After sound generator is enabled, it will start to count down. When it counts to zero, the it will

count from the initial value again.
* Valid values are from 1 to 255. Zero is prohibited.

LCD Controller 7 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

Bit 1(3) of $1013

* The time elapse = ($1011)/timer clock/2

1012 Sound generator 2 data. Write only.

* Before writing $1012, the program should select timer clock ($1010) first.
* After sound generator is enabled, it will start to count down. When it counts to zero, it will count

from the initial value again.
* Valid values are from 1 to 255. Zero is prohibited.
* The time elapse = ($1012)/timer clock/2

1013 Sound channel control register. Write only.

Bit 0 : = 0 Disable sound generator 1.

= 1 Enable sound generator 1.

1 : = 0 Set SOUND 1 to CMOS output pin.

STK55C324

= 1 Set SOUND 1 to sound channel 1 DAC output.

2 : = 0 Disable sound generator 2.

= 1 Enable sound generator 2.

3 : = 0 Set SOUND 2 to CMOS output pin.

= 1 Set SOUND 2 to sound channel 2 DAC output.

The default values for each bit is zero.
Please follow the item 6.4 for sound channel operation.

Bit 1 of $1008($1009)

Sound generator output

Bit 0(2) of $1013

0

$1008($1009)

S

0

OUT D/A

1

0

1

OUT

SOUND1(2)

S

6. FUNCTION DESCRIPTION

6.1 The reset state of control registers:
Address Value after reset

$1002
$1003

LCD Controller 8 /24 Issue date: 13 August, 1999

XXX00000
XXXXX000

Syntek Semiconductor Co., Ltd.

STK55C324

$1004
$1005
$1008

$1009
$100C
$100D

$100E
$100F

$1010

$1011

$1012

$1013

6.2 The reset status of CPU

If the /RES is keep low more than two system clocks, then the CPU will be reset. After reset, the interrupt

XXH

00H
XXXXXX0X
XXXXXX0X

00H

XXH

FXH

00H

XXH

XXH

XXH

00H

mask flag is set, the decimal mode is cleared and the program counter will be loaded with the reset vector
from address $FFFC and $FFFD. So, after initial procedure the firmware should do a ‘CLI’
instruction . Otherwise, the CPU will not acknowledge any interrupt.

6.3 Interrupt Sources

* There are five interrupt sources :

NMI - 64 Hz interrupt.
IRQ1 - Fix-time timer interrupt.
IRQ2 - Timer interrupt.

IRQ3 - Port 1 interrupt.
* All interrupts will wake up CPU from standby mode.
* NMI, IRQ1 and IRQ3 will wake up CPU from sleep mode 2.
* Only IRQ3 will wake up CPU from sleep mode 1.
* When port 1 is in input mode and pin interrupt enable, a low signal from pin will generate IRQ3.
* When the CPU acknowledge the interrupt, following things will be done:

a) The interrupt mask flag will be set by CPU
b) The return address and status register will be pushed to stack.

* When the CPU return from interrupt routine by RTI instruction following things will be done:

a) The return address and status register will be pulled from stack.
b) The interrupt mask flag will be cleared.

LCD Controller 9 /24 Issue date: 13 August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

* It is not necessary to add SEI and CLI instructions in interrupt routine. If a CLI instruction is added

in the interrupt routine, then another interrupt may be inserted during current interrupt routine and may

cause stack overflow.

6.4 Sound channel operation :

6.4.1 If two sound channels are used and the SOUND1 and SOUND2 are tied together, then please follow
below instructions to make two sound channels work.

1). All channels off.

a. Set $1013 to zero.
b. Set $1008 and $1009 to zero .

2). Channel 1 output tone and channel 2 output voice or turn off .

a. Set $1013 to 0BH.
b. Set $1009 to zero to turn off or set the volume according to the voice data.
c. Set $1008 to the desired volume.
d. Set sound generator to the desired frequency.

3). Channel 2 output tone and channel 1 output voice or turn off.

a. Set $1013 to 0EH.
b. Set $1008 to zero to turn off or set the volume according to the voice data.
c. Set $1009 to the desired volume.
d. Set sound generator to the desired frequency.

4). Channel 1 output voice or turns off and channel 2 output voice or turns off.

a. Set $1013 to 0AH.
b. Set $1009 to zero to turn off or set the volume according to the voice data..
c. Set $1008 to zero to turn off or set the volume according to the voice data.
Note : If both of these two channels are off, then $1013 should be set to zero. (see item 1)

5). Two channels output tone.

a. Set $1013 to 0FH.
b. Set $1008 and $1009 to the desired volumes.
c. Set sound generators to the desired frequency.

6.4.2 If only one channel is used or two channels are used but they are not tied together, then follow below
instructions.

1). Channel off.

a. Set SOUND output to CMOS output (bit 1 or bit 3 of $1013 to zero).
b. Set volume to zero ($1008 or $1009).

2). Channel output tone.

a. Set SOUND output to DAC output (bit 1 or bit 3 of $1013 to one).
b. Set sound generator to the desired frequency.
c. Set the channel volume ($1008 or $1009).
d. Enable sound generator (bit 0 or bit 2 of $1013 to one).

3). Channel output voice.

a. Set SOUND output to DAC output (bit 1 or bit 3 of $1013 to one).
b. Disable sound generator (bit 0 or bit 2 of $1013 to zero).

LCD Controller 10 /24 Issue date: 13 August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

c. Set the volume according to the voice data ($1008 or $1009).

7. ABSOLUTE MAXIMUM RATINGS

Operating temperature ........................................................................ 0 to 70 ℃

Storage temperature ...................................................................... -65 to 150 ℃

Supply voltage ............................................................................................... 7 V

Input voltage ........................................................................... -0.6 to Vdd+0.6 V

LCD Controller 11 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

V

MHz

Hz

A

AµA

AµAµAµA

AµAµAµA

V

V

A

A

V

V

V

V

8. ELECTRICAL CHARACTERISTIC :

Parameter Symbol Condition Min Typ. Max Unit

Supply Voltage Vdd 2.5 3.0 5.5
Main system frequency ∅sys Vdd=2.7V 0.1 1 2
Crystal frequency ∅cry 32768

STK55C324

Operating current Idd Vdd=3V,∅sys=120Khz

Vdd=3V,∅sys=1Mhz

Sleep mode 1 current Islp1 Vdd=3V, LCD off

Vdd=5V, LCD off
Sleep mode2 current
(32768KHz using crystal)

Sleep mode2 current
(32768KHz using RC)

Input high voltage Vih Vdd=5.0V 2.0
Input low voltage Vil Vdd=5.0V -0.6 0.8
Input high leakage current Iih Vih=Vdd -1 µ
Input low leakage current Iil Vil=0V 1 µ

Islp2 Vdd=3V,LCD on

Vdd=3V,LCD off

Vdd=5V, LCD on

Vdd=5V, LCD off

Islp2 Vdd=3V,LCD on

Vdd=3V,LCD off

Vdd=5V,LCD on

Vdd=5V,LCD off

120
1

0.2

0.5
15
4
65
15
25
8
87
31

mA

µ

µ

µ

µ

Output high voltage
(For SEGx and COMx)
Output low voltage
(for SEGx and COMx)
Output high voltage
(for other pins)
Output low voltage
(for other pins)

LCD Controller 12 /24 Issue date: 13 August, 1999

Voh1 Ioh=-30µA Vlcd

-0.2

Vol1 Iol=40µA 0 0.2

Voh2 Ioh=-2mA Vdd-

0.4

Vol2 Iol=2mA 0 0.4

Vlcd

Vdd

2.0uA

1.5uA

1.0uA

Islp1

0.5uA

0.0uA

STK55C324

Syntek Semiconductor Co., Ltd.

Sleep mode 1 current

2V 3V 4V 5V 6V

Vdd

150uA
100uA

Islp2

30uA
20uA

Islp2

10uA

Sleep mode 2 (LCD on, 32768KHz crystal)

50uA

0uA

2V 3V 4V 5V 6V

Vdd

Sleep mode 2 (LCD off, 32768KHz crystal)

0uA

2V 3V 4V 5V 6V

Vdd

LCD Controller 13 /24 Issue date: 13 August, 1999

10

5

fsys (Mhz)

0

2V 3V 4V 5V 6V

STK55C324

Syntek Semiconductor Co., Ltd.

Max. operating frequency

Vdd

LCD Controller 14 /24 Issue date: 13 August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

9. LCD WAVEFORM :

1/64 sec

Vlcd

3/4 Vlcd

COM0 2/4 Vlcd

1/4 Vlcd

Vss

Vlcd

3/4 Vlcd

COM1 2/4 Vlcd

1/4 Vlcd

Vss

Vlcd

3/4 Vlcd

COM2 2/4 Vlcd

1/4 Vlcd

Vss

•

•

•

Vlcd

3/4 Vlcd

COM7 2/4 Vlcd

1/4 Vlcd

Vss

Vlcd

3/4 Vlcd

SEGx 2/4 Vlcd

1/4 Vlcd

Vss

There are two LCD matrix DOTs active at (SEGx,COM1) and (SEGx,COM7)

LCD Controller 15 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

10. PAD LOCATION :

STK55C324

Chip size : 2090 x 2210 Unit : µM

PAD-No Name X Y PAD-No Name X Y

1 CONTRAST 106.37 2147.50 34 SEG26 1983.64 62.50
2 COM2 63.64 2027.50 35 SEG27 2026.37 187.50
3 COM3 63.64 1907.50 36 SEG28 2026.37 307.50
4 COM4 63.64 1787.50 37 SEG29 2026.37 427.50
5 COM5 63.64 1667.50 38 SEG30 2026.37 547.50
6 COM6 63.64 1547.50 39 SEG31 2026.37 667.50

LCD Controller 16 /24 Issue date: 13 August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

PAD-No Name X Y PAD-No Name X Y

7 COM7 63.64 1427.50 40 SEG32 2026.37 787.50
8 SEG0 63.64 1307.50 41 SEG33 2026.37 907.50

9 SEG1 63.64 1187.50 42 SEG34 2026.37 1027.50
10 SEG2 63.64 1067.50 43 SEG35 2026.37 1147.50
11 SEG3 63.64 947.50 44 SEG36 2026.37 1267.50
12 SEG4 63.64 827.50 45 SEG37 2026.37 1387.50
13 SEG5 63.64 707.50 46 SEG38 2026.37 1507.50
14 SEG6 63.64 587.50 47 SEG39 2026.37 1627.50
15 SEG7 63.64 467.50 48 XOSC2 2026.37 1747.50
16 SEG8 63.64 347.50 49 XOSC1 2026.37 1867.50
17 SEG9 63.64 227.50 50 RESL 2026.37 1987.50
18 SEG10 63.64 107.50 51 OSC2 2026.37 2107.50
19 SEG11 183.64 62.50 52 OSC1 1906.37 2147.50
20 SEG12 303.64 62.50 53 VDD 1786.37 2147.50
21 SEG13 423.64 62.50 54 PORT10 1666.37 2147.50
22 SEG14 543.64 62.50 55 PORT11 1546.37 2147.50
23 SEG15 663.64 62.50 56 PORT12 1426.37 2147.50
24 SEG16 783.64 62.50 57 PORT13 1306.37 2147.50
25 SEG17 903.64 62.50 58 PORT14 1186.37 2147.50
26 SEG18 1023.64 62.50 59 PORT15 1066.37 2147.50
27 SEG19 1143.64 62.50 60 PORT16 946.37 2147.50
28 SEG20 1263.64 62.50 61 PORT17 826.37 2147.50
29 SEG21 1383.64 62.50 62 VSS 706.37 2147.50
30 SEG22 1503.64 62.50 63 SOUND2 586.37 2147.50
31 SEG23 1623.64 62.50 64 SOUND1 466.37 2147.50
32 SEG24 1743.64 62.50 65 COM0 346.37 2147.50
33 SEG25 1863.64 62.50 66 COM1 226.37 2147.50

LCD Controller 17 /24 Issue date: 13 August, 1999

Syntek Semiconductor Co., Ltd.

1. APPLICATION CIRCUIT :

S10

S9C0S7

S8

S6

S5

S4

S3

S2

STK55C324

Note : The value of R1 is from 0 to 500K ohm for external

contrast control and can be omitted.

C4

C5

C3

C2

C6

C7

S0

S1

S[0-39]
C[0-7]

Note : R3 can be deleted.

VCC

R3
150K

C1

0.1u

S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26

S1

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26

8

5

6

7

9

10

11

12

13

14

15

16

17

18

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG2735SEG2836SEG2937SEG3038SEG3139SEG3240SEG3341SEG3442SEG3543SEG3644SEG3745SEG3846SEG39

S31

S34

S30

S32

S33

S35

Y1
32768Hz

S27

C2

22p

C3

S28

S29

S36

S37

COM6

COM7

47

S39

S38

COM5

48

2

3

4

COM2

COM3

COM4

CONTRAST

COM1

COM0
SOUND1
SOUND2

VSS
PORT17
PORT16
PORT15
PORT14
PORT13
PORT12
PORT11
PORT10

VDD

OSC1

XOSC1

XOSC2

RESL

OSC2

49

50

51

U1
KC5732

1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

R5
560K

For RC

C1

R2
24K

R1

R

VCC

XOSC1

XOSC2

VCC

VCC

R4
R

Note : R4 is for volume control and can be omitted.

LS1

SPEAKER

Q1
2N8050

22p

For crystal

Title

Application circuit

Size Document Number Rev

KC5732 A

A

Date: Sheet of

LCD Controller 18 /24 Issue date: 13 August, 1999

1 1Monday, May 24, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

User guide for STK55C322/324 emulator

1. Connectors :

1.1 J1 is a phone jack connector. Please connect to a voltage adapter with 7 Vdc output.

1.2 JP1 and JP2 should be connected to external LCD panel or LCD simulator.

1.3 JP3 is I/O port connector.

1.4 JP4 is for external speaker.

2. Switch setting :

2.1 S1 set the CPU compatible to standard CPU or KC5713 CPU.

2.2 S2 select internal CPU or external CPU.

INT. CPU – In this mode, the internal CPU is enabled. The external CPU or ICE

should be removed.

EXT. CPU – In this mode, the internal CPU is disabled. An external CPU or ICE

should be installed in U1.

2.3 S3 is power switch for EV chip.

IC ON – The Vcc is connected to the KC5731 IC.
IC OFF -- The Power pin of KC5731 IC is floating. The IC operating current can be

measured by connecting a current meter between the two points of TP2 or
between J7 and J8.

2.4 S4 is oscillator selection switch.

XTAL -- Use 32768HZ crystal oscillator.
RC -- Use RC oscillator. R3 will decide the oscillation frequency. In this mode, the

Y1 crystal should be removed. The frequency can be checked at XOSC2.

2.5 S5 is reset switch.

2.6 S6 is speaker selection switch.

INT. SPK -- On board speaker is selected.
EXT. SPK -- External speaker is selected. The customer’s speaker can be add

between J9 and J11.

2.7 S7 is power switch.

EXT. PWR -- Add DC power from J2 (GND) and J3 (Vdd). The voltage range is

LCD Controller 19 /24 Issue date: 13
August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

from 2.2V to 5.5V.

REG. PWR -- Add an adapter to J1. The system power is through the LM7805

voltage regulator.

LCD Controller 20 /24 Issue date: 13
August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

2.8 S8 is power switch for the emulator.

ON -- Normal operation.
OFF-- Add a current meter between TP3 or between J5 and J6 to measure the current

of whole system.

3. Others :

3.1 TP1 – The CPU clock. The R2 will decide the CPU operating frequency. A small value

will get a higher frequency.

3.2 The user program EPROM should be installed in U2.

3.3 The user program area is from 8000H-FFFFH.

3.4 The pull-up resistors should be added externally. The resistance of pull-up should be

greater than 200K ohm.

3.5 SOUND1 is used to drive speaker. If SOUND1 pin is used as an output, then please

cut the trace between U3-97 and the base of Q1. Then add a jumper wire from U3-97
to JP3-17.

4. Rework instructions for KP-2027 PCB.

4.1 Remove C3.

4.2 Isolate the left end of R3 from Vcc and add a jumper wire from the left end of R3 to

XOSC2.

4.3 Add a jumper wire from J7 to U3-77.

4.4 Add a jumper wire from U3-96 to JP3-19.

4.5 Add a jumper wire from U3-97 to JP3-17.

LCD Controller 21 /24 Issue date: 13
August, 1999

Syntek Semiconductor Co., Ltd.

STK55C324

U2

10

A0

A0

9

A1

A1

8

A2

A2

7

A3

A3

6

A4

A4

5

A5

A5

4

A6

A6

3

A7

A7

25

A8

A8

24

A9

A9

21

A10

A10

23

A11

A11

A12

2

A12

26

A13

A13

27

A14

A14

1

VCC

P10
P11
P12
P13
P14
P15
P16
P17

VCC

20
22

A15
CE

OE

27512

Note : 1. Remove C3 .

11

O0

12

O1

13

O2

15

O3

16

O4

17

O5

18

O6

19

O7

JP3

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

HEADER 17X2

2. One end of R3 change
from Vdd to XOSC2.

J1

PHONEJACK

D1

DIODE

D4

DIODE

D0
D1
D2
D3
D4
D5
D6
D7

D2

DIODE

D5

DIODE

TP1

CPU CLK

U1

VCC

C3
10p

VOUT

GND

D0
D1
D2
D3
D4
D5
D6

D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10
A11
A12
A13
A14
A15

SYNC

PH1
PH2

WR
VPB
MLB

C1

22p
C2
22p

VDD

2

33

D0

32

D1

31

D2

30

D3

29

D4

28

D5

27

D6

26

D7

9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25

7
3
39
34
1
5

Y1
32768Hz

VCC

EXT PWR

REG PWR

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

S4

XTAL

RC

INT. CPU

EXT. CPU

VCC

IC ON

IC OFF

S7

S3

TP2

+ C5

S2

C4

0.1u

10u

R2
24K

S5

/RESET

D0
D1

ON

OFF

51

CPUSEL

52

ROMCE

53

SYNC

54

CPURES

55

A15

CADR15

A14

56

CADR14

57

A13

CADR13

58

A12

CADR12

59

A11

CADR11

A10

60

CADR10

61

A9

CADR9

62

A8

CADR8

63

A7

CADR7

A6

64

CADR6

65

A5

CADR5

66

A4

CADR4

67

A3

CADR3

68

A2

CADR2

69

A1

CADR1

70

A0

CADR0

71

RC

72

XOSC2

73

XOSC1

74

RES

75

OSC2

76

OSC1

77

VDD

78

RWB

79

CDATA0

80

CDATA1

Note : R4 is used to
adjust voice output
volume and quality.

TP3

S8

8

VDD

38

SO

R1
10K

40

RES

36

BE

37

PH0

4

IRQ

6

NMI

2

RDY

21

VSS

C6502

R3

620K

U4
LM7805

1

VIN

C6

+

10u

3

S1

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

41

37

38

39

40

42

43

44

45

46

47

50

NMI48IRQ49PH0

SEG34

SEG31

SEG32

SEG33

SEG35

SEG36

SEG37

SEG38

SEG39

CPUCLI

CDATA4

CDATA3

CDATA6

CDATA7

CDATA5

CDATA281P1087P1188P1289P1390P1491P1592P1693P17

83

82

85

86

84

D2

R5

330

VCC

94

D7D6D5D4D3

P10

P11

P12

P13

P14

P15

P16

P17

D3
LED

STD CPU

KC5713 CPU

S29

S28

S27

S26

S25

S24

32

35

36

31

33

34

SEG25

SEG28

SEG29

SEG30

SEG24

SEG26

SEG27

30

SEG23

29

SEG22

28

SEG21

27

SEG20

26

SEG19

25

SEG18

24

SEG17

23

SEG16

22

SEG15

21

SEG14

20

SEG13

19

SEG12

18

SEG11

17

SEG10

16

SEG9

15

SEG8

14

SEG7

13

SEG6

12

SEG5

11

SEG4

10

SEG3

9

SEG2

8

SEG1

7

SEG0

6

COM7

5

COM6

4

COM5

3

COM4

2

COM3

1

COM2

VSS

COM0

COM1

CONTRAST

SOUND2

SOUND1

95

96

97

98

99

100

C0

C1

R4
R

U3
KC5731

S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
C7
C6
C5
C4
C3
C2

S6

INT SPK

EXT SPK

Q1
2N8050

Title

Emulator

Size Document Number Rev

STK55C322/324 A

B

Date: Sheet of

S0
S2
S4
S6
S8
S10
S12
S14
S16
S18
S20
S22
S24
S26
S28
S30
S32
S34
S36
S38

C1
C3

C7

VCC

VCC

JP1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

HEADER 30X2
JP2

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

HEADER 25X2

LS1

SPEAKER

J10

1
2

HEADER 2

S1
S3
S5
S7
S9
S11
S13
S15
S17
S19
S21
S23
S25
S27
S29
S31
S33
S35
S37
S39

C0
C2
C4C5
C6

1 1Monday, June 21, 1999

VCC

LCD Controller 22 /24 Issue date: 13
August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

Customer Information Sheet for STK55C322/324 990524

1. Customer's Name : ____________________

2. Project title : _________________________

3. Syntek part number : ___________________ (will be filled by Syntek.)

4. Package --------------------------------- ( ) Chip ( ) QFP

5. Options :
LCD display clock ----------- ( ) RC ( ) 32768Hz crystal

P o r t 1

7 6 5 4 3 2 1 0

Pull-up

6. Customer code :

Code form ----------------- ( ) EPROM ( ) file _______________
Checksum ----------------- 8000-9FFF __________H

A000-BFFF __________H
C000-DFFF __________H
E000-FFFF __________H
8000-FFFF __________H

7. Operating conditions :

All the operating conditions listed below are for Syntek reference. Syntek will not
guaranty on these values. Please refer to data book or contact Syntek for the guaranty

values.
Operating voltage : _____-_____ V
Operating current : _____ mA Operating frequency : _____ Hz
Sleep current :

Mode 1 : _____ µA (LCD off)
Mode 2 : _____ µA (LCD on), _____ µA (LCD off)

LCD Controller 23 /24 Issue date: 13
August, 1999

STK55C324

Syntek Semiconductor Co., Ltd.

Customer : __________________ Salesman : __________________Date : __/__/__

Check List before release the code to mask

Item YES NO Check item Action

1 No problem is found in internal CPU

mode.

2 The operating current is acceptable Set S3 off. Measure the

3 The sleep current is acceptable. Same as item 2.
4 The CPU frequency is correct. Check TP1.
5 The 32768Hz frequency is correct Check XOSC2.
6 The pull-up resistance is greater than

200K ohm.

Set S2 to INT. CPU and run
the program.

current on TP2.

LCD Controller 24 /24 Issue date: 13
August, 1999