Page 1
LCD Controller 1/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Specification
1. CHIP FEATURES :
* Operating voltage : 2.5V-4.5V
* Dual operation frequencies :
- 32.768 KHz for LCD & 0.5 second timer interrupt.
- Built-in PLL circuit to generate system clock.
* Built-in 2K bytes RAM.
* Built in 192x8 display RAM for LCD data.
* Built-in 512K bytes ROM with 16K bytes per bank.
* External memory can be expanded to two 1M bytes ROM/RAM with 16K bytes per
bank.
* One 0.5 second pre-divider timer interrupt with start/stop control.
* I/O ports
- 14 pins shared with address bus for keyboard output port 1 and port 2.
- 4 input pins with wake-up interrupt for port 3. Pull-up resistors are built-in for this port.
- 8 I/O pins shared with D0-D7 for port 4.
- 8 I/O pins for port 5.
* 8-bit auto-reloadable timer with 8 predefined input clocks.
* 8-bit sound generator with 8 predefined input clocks.
* LCD display : 48 segments, 32 commons, 1/5 bias, 1/32 duty and 64 Hz frame
frequency.
* 16 contrast levels for LCD display
* One output for the speaker.
- 2 KHz or 4 KHz signal with two different envelopes are selectable for sound output.
* One UART serial port with even parity bit and one stop bit added after MSB. A carrier
generator is also built-in.
* The internal ROM can be disabled and the corresponding memory area is mapped to the
highest banks of external ROM.
* Sleep mode : LCD off , crystal & system oscillator stop, Vdd=3V, Idd < 1 µA.
Stand-by mode : LCD on and system oscillator stop, Vdd=3V, Idd < 200 µA.
LCD off and system oscillator stop, Vdd=3V, Idd < 10 µA.
Page 2
LCD Controller 2/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
* Code option :
- 150K OHM Pull-up resistor for P40-P47 and P50-P57
- RC or crystal oscillation for 32768Hz clock.
2. APPLICATION:
l Data Bank
l Translator
l Organizer
l Hand-held game
Page 3
LCD Controller 3/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
3. BLOCK DIAGRAM:
A0-A15
D0-D7
A0-A13 P30-P33 P50-P57 D0-D7
8-bit CPU
Address
decoder
ROM
512Kx8
RAM
2Kx8
Clock
Generator
LCD driver
Sound
generator
Port 1, 2
PLL
SOUND
32768Hz
C0-C31
S0-S47
UART
MUX
16-bit Timer
TX
RX
Port 5
Port 3
MUX
Port 4
Bank control
B0-B6
Page 4
LCD Controller 4/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
4. PIN DESCRIPTION : (Total 136 pads)
Pin name I/O Description
COM0-COM31 O Output pins for driving the commons of LCD panel
SEG0-SEG47 O Output pins for driving the segments of LCD panel
SOUND O Output pin for speaker
P10-P17 O Output port 1. These pins will change to address bus A0-
A7 during external memory access cycles.
P20-P25 O Output port 2. These pins will change to address bus A8-
A13 during external memory access cycles.
P30-P33 IU 4 input pins for key matrix with wake-up interrupt.
P40-P47 I/O I/O port 4. These pins will change to data bus D0-D7
during external memory access cycles.
CAP I/O Low pass filter capacitor for PLL circuit.
/RES IU Chip reset
VDD I Power input
VSS I Signal ground
XOSC1 I Crystal oscillator input pin
XOSC2 O Crystal oscillator output pin
BANK0-BANK5 O External memory bank select outputs. Usually, the bank
value for /CE1 is output in BANK0-BANK5 except the
cycle for accessing /CE2.
/CE1 O External memory chip enable 1. This pin will keep high
during sleep or standby mode.
/CE2 O External memory chip enable 2. This pin will keep high
during sleep or standby mode.
RWB O Read/Write signal output
VLCD I Power supply for LCD driver
VCAP I/O Connect a capacitor between this pin and F256 for voltage
doubler.
F256 O 256 Hz output clock for voltage doubler. This clock will be
stopped if 32.768K Hz crystal is stopped
/DIROM IU Internal ROM control pin.
=0 Disable internal ROM
=1 Enable internal ROM
P50-P57 I/O Port 5.
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LCD Controller 5/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Pin name I/O Description
/PCE O Chip enable signal for $2030-$203F. This pin is shared
with P52.
TX O Transmit data pin. This pin is shared with P50.
RX IU Receive data pin. This pin is shared with P51.
/TEST IU Test pin. Keep floating or connect to Vcc.
CONTRAST I LCD contrast control input.
Note : IU -- Input pin with pull-up resistor.
5. ADDRESS ARRANGEMENT :
1) RAM
0000-00FF for zero page area.
0100-01FF for stack and data page area.
0200-07FF for data area.
3000-30BF LCD display data area.
SEG0-SEG7 SEG8-SEG15 • • • SEG40-SEG47
COM0 3000 3020 • • • 30A0
COM1 3001 3021 • • • 30A1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM31 301F 303F 30BF
2) ROM
4000-7FFF For external memory chip 1. While CPU access this area, the /CE1 will be
low. But the /CE1 will be kept high during sleep and standby mode.
8000-BFFF For external memory chip 2 or internal ROM bank. The /CE2 will be kept
high during sleep and standby mode.
/DIROM Bit 1 of $201A Function description
0 1 This area is external memory. /CE2 will be low and
the data in $200A will output to BANK0-BANK5.
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LCD Controller 6/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
X 0 This area is external memory. /CE2 will be low and
the data in $200A will output to BANK0-BANK5.
1 1 This area is internal ROM and the bank number is
defined by $200A. /CE2 keeps high.
C000-FFFF : for program
/DIROM Function description
0 This area is external memory. /CE2 will be low and BANK5-
BANK0=3FH.
1 This area is the last bank of internal ROM. /CE2 keeps high.
The /CE2 will be kept high during sleep and standby mode.
FFFF, FFFE - IRQ vector.
FFFD, FFFC - RES vector.
FFFB, FFFA - NMI vector.
3) Others
2000 To enter stand-by mode; write only.
* In standby mode, the system oscillator will be stopped. But 32768Hz crystal
will still work.
* The CPU, UART and timer will be stopped.
* LCD state is depended on bit 1 of $200D.
* NMI and IRQ3 are still functionally.
* When in stand-by mode, NMI, IRQ2, IRQ3 or IRQ6 will wake up the CPU.
2001 To enter sleep mode; write only.
* In sleep mode, whole chip will be stopped. That is, the system and 32768 Hz
crystal oscillator will be stopped.
* The LCD display will be turned off.
* Only reset, IRQ2 and IRQ6 can wake up this chip.
* When CPU frequency = 32768 Hz ($2006 = 0), do NOT go into sleep mode
2002 Sound output control. Write only.
Bit 0 : = 0 For 2 KHz base frequency
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LCD Controller 7/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
= 1 For 4 KHz base frequency
2-1 : = 0x Sound off
= 10 For alarm envelope
= 11 Sound always on
* The default value for each bit is zeros.
Alarm envelope waveform: (unit = second)
2003 IRQ flag register; read & write.
* Read : Bit 0 : if 1, timer interrupt, IRQ1.
Bit 1 : if 1, port 3 interrupt, IRQ2.
Bit 2 : if 1, 0.5 sec. timer interrupt, IRQ3.
Bit 3 : if 1, transmit data complete interrupt, IRQ4.
Bit 4 : if 1, receiver data ready interrupt, IRQ5.
Bit 5 : if 1, Port 5 interrupt, IRQ6. This flag will be read as ‘1’ if
any pin of port 5 generates interrupt.
* Write : Bit 0 : if 1, clear the flag of IRQ1.
Bit 1 : if 1, clear the flag of IRQ2.
Bit 2 : if 1, clear the flag of IRQ3.
Bit 3 : if 1, clear the flag of IRQ4.
Bit 4 : if 1, clear the flag of IRQ5.
* Before firmware exits the interrupt routine, the interrupt flag must be cleared.
Otherwise, the IC will get into interrupt again.
* Write 1 to clear the corresponding IRQ but do not write 0FFH to clear all
interrupts at the same time.
* Do NOT use TSB to test and clear this register. Following instructions are
recommended.
LDA $2003
AND #1 ;Check IRQ 1
1/4
10/16
1/16
1/16
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LCD Controller 8/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
BEQ next_irq
STA $2003 ;Clear the active interrupt.
2004 Port 5 interrupt flag register; read & write.
* Read : If any pin of port 5 generates interrupt, then the corresponding bit in
this register will be read as ‘1’.
* Write : If an ‘1’ is written to this register, then the interrupt flag of the
corresponding pin will be cleared.
* Port 5 interrupt is edge trigger interrupt. But once the interrupt is triggered,
then the interrupt will be always active until this register is cleared,.
* Before firmware exits the interrupt routine, the interrupt flag must be cleared.
Otherwise, the IC will get into interrupt again.
2005 LCD contrast level. Write only.
Bit 3-0 : Reserved.
7-4 : Contrast level. ‘0’ is the minimum contrast and ‘F’ is the maximum
contrast.
The default state is at the maximum contrast.
2006 Set CPU operating frequency. Write only.
Bit 2-0 : = 000 System clock = Fxosc
= 001 System clock = Fxosc X 16
= 010 System clock = Fxosc X 32 (default)
= 011 System clock = Fxosc X 48
= 100 System clock = Fxosc X 64
= 101 System clock = Fxosc X 72
= 110 System clock = Fxosc X 96
= 111 System clock = Fxosc X 128
7-3 : Reserved.
Fxosc is the oscillation frequency on XOSC1 and XOSC2. The CPU will be halt
for four system cycles after system clock change or wake-up from sleep
/standby mode. After wake up from sleep/standby mode, it will take about 20ms to
make the system clock stable. So, the software should delay at least 20ms before
output the melody/voice data or send/receive data to/from UART.
2007 Port 3 data; read only
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LCD Controller 9/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Bit 3-0 : Input data.
Two wait states will be added while CPU read this port.
2008 Set port 3 bit interrupt function; write only.
* An '0' in this register will set the interrupt function of the corresponding pin of
port 3 to be enabled.
* If port 3 are used as key inputs, there are several interrupts will be generated
during key pressing or release. This is caused by key bounce. It is suggested to
disable the port1 interrupt after port 3 interrupt is detected and enable the port
3 interrupt after key released. Or enable port 3 interrupt before entering sleep
or standby mode and disable port 3 interrupt after IC wakeup..
* The default value for each bit is one.
2009 Set bank of external memory chip 1; write only
Bit 5-0 : Bank value
200A Set bank of external memory chip 2 or internal ROM bank; write only
Bit 4-0 : External memory or internal ROM bank.
5 : External memory bank.
200B Timer clock select. Write only.
Bit 2-0 : Timer 1 clock select.
= 000 Fxosc
= 001 System clock/4
= 010 System clock/8
= 011 System clock/16
= 100 System clock/32
= 101 System clock/64
= 110 System clock/128
= 111 System clock/256
3 : Reserved
Bit 6-4 : Sound generator clock select.
= 000 Fxosc
= 001 System clock/4
= 010 System clock/8
= 011 System clock/16
= 100 System clock/32
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LCD Controller 10/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
= 101 System clock/64
= 110 System clock/128
= 111 System clock/256
7 : Reserved
Fxosc is the oscillation frequency on XOSC1 and XOSC2.
The default value is unknown.
200C Write initial timer value; Write only.
* Timer 1 IRQ frequency = input clock/ [($200C)+1]
* Valid values are from 1 to 255. Zero is prohibited.
200D Control register; write only
Bit 0 : = 0 Disable 64 Hz NMI
= 1 Enable 64 Hz NMI
1 : = 0 LCD off
= 1 LCD on
2 : = 0 Disable timer
= 1 Enable timer
3 : = 0 Disable IRQ1
= 1 Enable IRQ1
4 : = 0 P52 is I/O pin.
= 1 P52 is /PCE external chip select pin.
5 : = 0 P50-P51 are I/O pins
= 1 P50 is UART transmit data pin
P51 is UART receive data pin
The default value is zero.
200E 0.5 sec timer interrupt; write only
Bit 0 : = 0 Stop 0.5 second timer and reset it. (default)
= 1 Start 0.5 second timer
The IRQ3 will occur every 0.5 sec.
200F Port 5 data. Read and write.
2010 Set port 5 function; write only.
* An '1' in this register will set the corresponding pin of port 5 to be output.
* The default value for each bit is zeros.
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LCD Controller 11/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
2011 Set port 5 bit interrupt function; write only.
* An '0' in this register will set the interrupt function of the corresponding pin of
port 5 to be enabled.
* If any pin of port 5 is set as output, then the interrupt function of that pin is
always disabled not matter whether the corresponding bit of this register is one
or not.
* The default value for each bit is one.
2012 Output data for keyboard output port 1. Write only.
2013 Output data for keyboard output port 2. Write only.
Bit 5-0 : Keyboard output port2 data.
2014 Load baud rate counter value ; write only.
Baud rate = (system clock)/16/[$2014]
* Valid values are from 1 to 255. Zero is prohibited.
Example: For Fxosc=32768Hz
Baud rate System frequency Counter Value (Dec) Actual Baud rate Error (%)
1200 Fxosc X 64 109 1202.5 0.21
2400 Fxosc X 64 54 2427.26 1.14
3600 Fxosc X 64 36 3640.89 1.14
4800 Fxosc X 64 27 4854.52 1.14
7200 Fxosc X 64 18 7281.78 1.14
9600 Fxosc X 64 14 9362.29 -2.48
19200 Fxosc X 64 7 18724.57 -2.48
1200 Fxosc X 72 123 1198.83 -0.1
2400 Fxosc X 72 61 2417.31 0.72
4800 Fxosc X 72 31 4756.65 -0.9
9600 Fxosc X 72 15 9830.4 2.4
19200 Fxosc X 72 8 18432 -4
19200 Fxosc X 96 10 19660.8 2.4
2015 Set UART carrier generator value. Write only.
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LCD Controller 12/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Carrier frequency = (system clock)/2/[$2015]
* Valid values are from 1 to 255. Zero is prohibited.
2016 Read : read the received data from buffer
Write: load data to buffer for transmission
2017 UART status register; read & write.
Bit 0 : = 0 Received data no error
= 1 Received data parity error
1 : = 0 Transmit buffer not ready
= 1 Transmit buffer empty
2 : = 0 Disable carrier generator.
= 1 Enable carrier generator.
7-3 : Reserved.
* Bit 0 and bit 1 are read only.
System clock
Bit 2 of $2017
TX_data
2019 Write initial value to sound generator; write only
* Output frequency = input clock/ [($2019)+1]/4
* Valid values are from 1 to 255. Zero is prohibited.
201A Control register. Write only.
Bit 0 : = 0 Enable external memory expansion. A0-A13 are shared with
port 1 and port 2. D0-D7 are data bus.
= 1 Disable external memory expansion. $8000-$BFFF are internal
ROM. A0-A13 are output port 1 and port 2. D0-D7 are port
4.
1 : = 0 $8000-$BFFF are external ROM bank.
= 1 $8000-$BFFF are internal ROM bank.
2 : Reserved.
3 : = 0 Select alarm clock output.
= 1 Select sound generator output.
4 : = 0 Disable sound generator.
8-bit counter
(Carrier Gen.)
TX pin
AND
OR
1/2
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LCD Controller 13/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
= 1 Enable sound generator.
5 : = 0 Allow sound generator output to SOUND pin.
= 1 Set sound generator output to high.
7-6 : Reserved.
The default value is zero.
201B Volume control for sound generator. Write only.
Bit 7-0 : Volume value. Zero is the minimum volume.
Bit 5 of $201A
Bit 3 of $201A
Bit 2 of $2002
Bit 0 of $2002
2K Hz alarm clock
4K Hz alarm clock
Sound generator output
0
$201B
2020 Port 4 data. Read and write.
2021 Set port 4 function; write only.
* An '1' in this register will set the corresponding pin of port 4 to be output.
* The default value for each bit is zeros.
2024 Port 5 interrupt control register. Write only.
* An ‘1’ in this register will set the corresponding pin of port 5 to generate an
interrupt on the rising edge. Otherwise, the interrupt will be generated in the
falling edge.
S
0
1
MUX S
0
1
MUX
SOUND
OR
S
0
1
MUX
AND
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LCD Controller 14/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
* The default value for each bit is zeros.
2030-203F External device chip enable. Read & write.
* While CPU access this area, the /PCE pin will output a low pulse.
* Do NOT use index addressing mode in this range. Otherwise, two pules will be
output to P52.
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LCD Controller 15/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
4) The reset status of CPU
If the /RES is keep low more than two system clocks, then the CPU will be reset.
After reset, the interrupt mask flag is set, the decimal mode is cleared and the
program counter will be loaded with the reset vector from address $FFFC and
$FFFD. So, after initial procedure the firmware should do a ‘CLI’ instruction.
Otherwise, the CPU will not acknowledge any interrupt.
5) Interrupts
* There are seven interrupt sources :
NMI - 64 Hz interrupt
IRQ1 - Timer interrupt
IRQ2 - Port 3 interrupts
IRQ3 - 0.5 second timer interrupt
IRQ4 - Transmit buffer ready interrupt
IRQ5 - Receiver data ready interrupt
IRQ6 - Port 5 interrupt
* Only reset, IRQ2 and IRQ6 will wake up CPU from sleep mode.
* Only IRQ2, IRQ3, IRQ6 and NMI can wake up CPU from stand-by mode.
* In the IRQ routine, the program should check $2003 to decide which Interrupt has
happened.
* When port 3 interrupt is enabled, a low signal from any pin will generate IRQ2.
* When the CPU acknowledge the interrupt, following things will be done:
a) The interrupt mask flag will be set by CPU
b) The return address and status register will be pushed to stack.
* When the CPU return from interrupt routine by RTI instruction following things will
be done:
a) The return address and status register will be pulled from stack.
b) The interrupt mask flag will be cleared.
* It is not necessary to add SEI and CLI instructions in interrupt routine. If a
CLI instruction is added in the interrupt routine, then another interrupt may be
inserted during current interrupt routine and may cause stack overflow.
6) Serial port
* Load baud rate counter value (by writing $2014) to counter to generate desired
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LCD Controller 16/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
baud rate.
* Write $2016 to transmit data, one byte at a time. When one data byte has been
transmitted, hardware generates IRQ4 interrupt (transmit buffer ready).
* When one data byte is received, hardware generates IRQ5 interrupt (receiver data
ready). Read $2016 to fetch data from buffer. The input data should be read before
next byte data complete received.
* Read $2017 bit 0 to check if data received is correct and read bit 1 to check when
next data byte can be transmitted.
* When system is in stand-by or sleep mode, serial port will be pending. So, please
make sure the serial data is transmitted completely before getting into standby or
sleep mode.
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LCD Controller 17/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
6. TIMING DIAGRAM FOR EXTERNAL MEMORY ACCESS :
6.1 Timing for external memory and external LCD driver access :
Description Symbol Min. Typ. Max. Unit
Cycle Time Tcyc 1500 nS
Address hold time Tah 10 nS
Address delay time Tads 100 nS
Delay time Tdr 10 nS
Write data delay time Tmds 100 nS
Write data hold time Tdhw 10 nS
Read data setup time Tdsr 40 nS
Read data hold time Tdhr 10 nS
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LCD Controller 18/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
6.2 Timing for read keyboard data :
7. I/O PIN STRUCTURE :
5.1 /DIROM pin :
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LCD Controller 19/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
8. ABSOLUTE MAXIMUM RATINGS :
Operating temperature ........................................................... 0 to 70℃
Storage temperature ......................................................... -65 to 150℃
Supply voltage ................................................................................. 7 V
Input voltage ............................................................ -0.6 to Vdd+0.6 V
9. ELECTRICAL CHARACTERISTIC :
Parameter Symbol Condition Min Typ. Max Unit
Supply Voltage Vdd 2.5 3.0 5.5 V
LCD Voltage Vlcd 5.0 7 V
Main system frequency ∅sys Vdd=2.5V
Vdd=5V
0.032
1.05
1.05 2.1
4.19
Mhz
Mhz
Crystal frequency ∅cry 32768 Hz
Operating current Idd Vdd=5V,∅sys=1Mhz 2 mA
Sleep mode 1 current Islp1 Vdd=5V,LCD off 1 µA
Sleep mode 2 current Islp2 Vdd=Vlcd=3V,LCD on
Vdd=Vlcd=3V,LCD off
Vdd=3V,Vlcd=5.4V,LCD on
Vdd=3V,Vlcd=5.4V,LCD off
Vdd=Vlcd=5V,LCD on
Vdd=Vlcd=5V,LCD off
15
5
45
5
50
15
µA
µA
µA
µA
µA
µA
Input high voltage Vih Vdd=5.0V 2.0 V
Input low voltage Vil Vdd=5.0V -0.6 0.8 V
Input high leakage current Iih Vih=Vdd -1 µA
Input low leakage current Iil Vil=0 1 µA
Output high voltage
(for other pins)
Voh2 Ioh=-4mA Vdd-
0.8
Vdd V
Output low voltage
(for other pins)
Vol2 Iol=4mA 0 0.8 V
5/5 bias voltage V1 Ioh=+/-100µA Vlcd-1 Vlcd V
4/5 bias voltage V2 Iol=+/-100µA 0.76 0.8 0.84 V1
3/5 bias voltage V3 Iol=+/-100µA 0.56 0.6 0.64 V1
2/5 bias voltage V4 Iol=+/-100µA 0.36 0.4 0.44 V1
1/5 bias voltage V5 Iol=+/-100µA 0.16 0.2 0.24 V1
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LCD Controller 20/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
10. LCD WAVEFORM :
1/64 sec
FR
V1
V2
V3
COM0 V4
V5
Vss
V1
V2
V3
COM1 V4
V5
Vss
V1
V2
V3
COM2 V4
V5
Vss
•
•
•
V1
V2
V3
COM31 V4
V5
Vss
V1
V2
V3
SEGx V4
V5
Vss
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LCD Controller 21/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
There are two LCD matrix DOTs active at (SEGx,COM1) and (SEGx,COM31)
11. PAD LOCATION:
Chip size : 4360 x 4710 Unit : µM
Pad No Name X Y Pad No Name X Y
1 VLCD 348.30 64.90 69 SEG35 4068.30 4635.30
2 COM0 468.30 64.90 70 SEG36 3948.30 4635.30
3 COM1 588.30 64.90 71 SEG37 3828.30 4635.30
4 COM2 708.30 64.90 72 SEG38 3708.30 4635.30
5 COM3 828.30 64.90 73 SEG39 3588.30 4635.30
6 COM4 948.30 64.90 74 SEG40 3468.30 4635.30
7 COM5 1068.30 64.90 75 SEG41 3348.30 4635.30
8 COM6 1188.30 64.90 76 SEG42 3228.30 4635.30
9 COM7 1308.30 64.90 77 SEG43 3108.30 4635.30
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LCD Controller 22/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Pad No Name X Y Pad No Name X Y
10 COM8 1428.30 64.90 78 SEG44 2988.30 4635.30
11 COM9 1548.30 64.90 79 SEG45 2868.30 4635.30
12 COM10 1668.30 64.90 80 SEG46 2748.30 4635.30
13 COM11 1788.30 64.90 81 SEG47 2628.30 4635.30
14 COM12 1908.30 64.90 82 SOUND1 2508.30 4635.30
15 COM13 2028.30 64.90 83 RESL 2388.30 4635.30
16 COM14 2148.30 64.90 84 DIROML 2268.30 4635.30
17 COM15 2268.30 64.90 85 P30 2148.30 4635.30
18 COM16 2388.30 64.90 86 P31 2028.30 4635.30
19 COM17 2508.30 64.90 87 P32 1908.30 4635.30
20 COM18 2628.30 64.90 88 P33 1788.30 4635.30
21 COM19 2748.30 64.90 89 P50 1668.30 4635.30
22 COM20 2868.30 64.90 90 P51 1548.30 4635.30
23 COM21 2988.30 64.90 91 P52 1428.30 4635.30
24 COM22 3108.30 64.90 92 P53 1308.30 4635.30
25 COM23 3228.30 64.90 93 P54 1188.30 4635.30
26 COM24 3348.30 64.90 94 P55 1068.30 4635.30
27 COM25 3468.30 64.90 95 P56 948.30 4635.30
28 COM26 3588.30 64.90 96 P57 828.30 4635.30
29 COM27 3708.30 64.90 97 CE1L 708.30 4635.30
30 COM28 3828.30 64.90 98 CE2L 588.30 4635.30
31 COM29 3948.30 64.90 99 RWB 468.30 4635.30
32 COM30 4068.30 64.90 100 VSS 348.30 4635.30
33 COM31 4202.30 64.90 101 TESTL 214.30 4635.30
34 SEG0 4293.95 279.95 102 P10 66.50 4442.85
35 SEG1 4293.95 404.95 103 P11 66.50 4316.85
36 SEG2 4293.95 529.95 104 P12 66.50 4190.85
37 SEG3 4293.95 654.95 105 P13 66.50 4064.85
38 SEG4 4293.95 779.95 106 P14 66.50 3938.85
39 SEG5 4293.95 904.95 107 P15 66.50 3812.85
40 SEG6 4293.95 1029.95 108 P16 66.50 3686.85
41 SEG7 4293.95 1154.95 109 P17 66.50 3560.85
42 SEG8 4293.95 1279.95 110 P20 66.50 3434.85
43 SEG9 4293.95 1404.95 111 P21 66.50 3308.85
Page 23
LCD Controller 23/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Pad No Name X Y Pad No Name X Y
44 SEG10 4293.95 1529.95 112 P22 66.50 3182.85
45 SEG11 4293.95 1654.95 113 P23 66.50 3056.85
46 SEG12 4293.95 1779.95 114 P24 66.50 2930.85
47 SEG13 4293.95 1904.95 115 P25 66.50 2804.85
48 SEG14 4293.95 2029.95 116 P40 66.50 2667.95
49 SEG15 4293.95 2154.95 117 P41 66.50 2539.50
50 SEG16 4293.95 2279.95 118 P42 66.50 2408.65
51 SEG17 4293.95 2404.95 119 P43 66.50 2280.15
52 SEG18 4293.95 2529.95 120 P44 66.50 2150.55
53 SEG19 4293.95 2654.95 121 P45 66.50 2020.95
54 SEG20 4293.95 2779.95 122 P46 66.50 1891.35
55 SEG21 4293.95 2904.95 123 P47 66.50 1761.75
56 SEG22 4293.95 3029.95 124 B0 66.50 1633.50
57 SEG23 4293.95 3154.95 125 B1 66.50 1499.90
58 SEG24 4293.95 3279.95 126 B2 66.50 1366.30
59 SEG25 4293.95 3404.95 127 B3 66.50 1232.70
60 SEG26 4293.95 3529.95 128 B4 66.50 1099.10
61 SEG27 4293.95 3654.95 129 B5 66.50 970.10
62 SEG28 4293.95 3779.95 130 CAP 66.50 839.50
63 SEG29 4293.95 3904.95 131 XOSC1 66.50 708.50
64 SEG30 4293.95 4029.95 132 XOSC2 66.50 577.50
65 SEG31 4293.95 4154.95 133 VDD 66.50 446.50
66 SEG32 4293.95 4279.95 134 F256 66.50 312.40
67 SEG33 4293.95 4404.95 135 VCAP 66.50 184.50
68 SEG34 4293.95 4524.95 136 CONTRAST 214.30 64.90
Page 24
LCD Controller 24/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
12. APPLICATION CIRCUIT :
Page 25
LCD Controller 25/25 Issue date: 2 April, 1999
Syntek Semiconductor Co., Ltd.
STK55C1500
Customer Information Sheet for STK55C1500 981028
1. Customer's Name : ____________________
2. Project title : _________________________
3. Syntek part number : __________________ (will be filled by Syntek)
4. Package ------------------------------- ( ) Chip ( ) QFP
5. Options :
32768Hz oscillator type ----------- ( ) RC ( ) XTAL
P o r t 4 P o r t 5
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Pull-up
6. Customer code :
Code form --------------- ( ) EPROM ( ) file _______________
Checksum --------------- 00000-1FFFF __________H
20000-3FFFF __________H
40000-5FFFF __________H
60000-7FFFF __________H
00000-7FFFF __________H
7. Operating conditions :
All the operating conditions listed below are for Syntek reference. Syntek will not
guaranty on these values. Please refer to data book or contact Syntek for the guaranty
values.
Operating voltage : _____-_____ V Voltage doubler : ( ) Yes ( ) No
Operating current : _____ mA Operating frequency : _____ Hz
Stand-by current : _____ µA (LCD on) _____ µA (LCD off)
Sleep current : _____ µA (LCD off)
Customer : __________________ Salesman : ___________________Date : __/__/__
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