Datasheet stk20n75f3 Datasheet

N-channel 75 V, 0.0065 Ω, 20 A, PolarPAK

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Features

Type

V

DSS

R

STK20N75F3 75 V < 0.0079 Ω

■ Ultra low top and bottom junction to case

thermal resistance

■ Extremely low on-resistance R

■

Very low switching gate charge

■ Fully encapsulated die

■ 100% matte tin finish (in compliance with the

DS(on)

2002/95/EC european directive)

■ High avalanche ruggedness

■ PolarPAK

®

is a trademark of VISHAY

DS(on)

max

STK20N75F3

STripFET™ Power MOSFET

PolarPAK

Figure 1. Internal schematic diagram

®

Application

■ Switching applications

Description

This STripFET™ III Power MOSFET technology is among the latest improvements, which have been especially tailored to minimize on-state resistance providing superior switching performances.

Bottom View

Top View

Table 1. Device summary

Order code Marking Package Packaging

STK20N75F3 20753

PolarPAK

®

Tape and reel

June 2009 Doc ID 14849 Rev 2 1/15

www.st.com

15

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Contents STK20N75F3

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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STK20N75F3 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

P

V

I

DM

TOT

DS

GS

D

I

D

Drain-source voltage (VGS = 0)

75 V

Gate-source voltage ± 20 V

(1)

Drain current (continuous) at TC = 25°C

Drain current (continuous) at TC = 100°C

(2)

Drain current (pulsed) 80 A

(1)

Total dissipation at TC = 25°C

20 A

12.5 A

5.2 W

Derating factor 0.0416 W/°C

(3)

E

AS

T

stg

1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10 sec

2. Pulse width limited by package

3. Starting TJ = 25 °C, ID = 20 A, VDD = 50 V

Single pulse avalanche energy 600 mJ

Operating junction temperature

j

Storage temperature

-55 to 150 °C

Table 3. Thermal data

Symbol Parameter Typ. Max. Unit

(1)

R

thj-amb

R

thj-c

R

thj-c

1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10sec

2. Steady state

3. Measured at source pin when the device is mounted on FR-4 board in steady state

Thermal resistance junction-amb 20 24 °C/W

(2)

Thermal resistance junction-case (top drain) 0.8 1 °C/W

(3)

Thermal resistance junction-case (source) 2.2 2.7 °C/W

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Electrical characteristics STK20N75F3

2 Electrical characteristics

(T

=25°C unless otherwise specified)

CASE

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Drain-source breakdown voltage

Zero gate voltage drain current (VGS = 0)

Gate body leakage current

= 0)

(V

DS

Gate threshold voltage

Static drain-source on resistance

= 250 µA, VGS= 0

I

D

V

= Max rating,

DS

V

= Max rating,Tc=125°C

DS

= ± 20V

V

GS

= VGS, ID = 250 µA

V

DS

VGS= 10 V, ID= 10 A

75 V

1

10µAµA

±100 nA

24V

0.0065 0.0079 Ω

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

C

Q

R

Input capacitance

iss

Output capacitance

oss

Reverse transfer

rss

capacitance

g

Total gate charge Gate-source charge

gs

Gate-drain charge

gd

Gate input resistance

G

=25 V, f=1 MHz, VGS=0

V

DS

= 38 V, ID = 20 A

V

DD

=10 V

V

GS

(see Figure 14)

f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain

2480

-

446

-

41

40.4

-

11.6

-

9.9

-0.85- Ω

pF pF pF

nC nC nC

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

= 37.5 V, ID= 10 A,

t

d(on)

t

d(off)

Turn-on delay time

t

Rise time

r

Turn-off delay time

t

Fall time

f

4/15 Doc ID 14849 Rev 2

DD

=4.7 Ω, VGS= 10 V

R

G

(see Figure 13)

VDD=37.5 V, ID= 10 A,

=4.7 Ω, VGS= 10 V

R

G

(see Figure 13)

15.6

-

16.2

37.8

4

ns

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STK20N75F3 Electrical characteristics

Table 7. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

Source-drain current

SD

Source-drain current

(1)

(pulsed)

(2)

Forward on Voltage

t

rr

Reverse recovery time Reverse recovery charge

rr

Reverse recovery current

I

SD

I

SD

V

DD

(see Figure 18)

I

SDM

V

I

SD

Q

RRM

1. Pulse width limited by package

2. Pulsed: pulse duration = 300µs, duty cycle 1.5%

= 20 A, VGS=0

= 20 A, di/dt = 100 A/µs,

=60 V, Tj=150°C

-

20 80

A A

-1.2V

49.7

-

103.6

4.2

ns

nC

A

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Electrical characteristics STK20N75F3

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance

I

D

(A)

100

Operation in this area is

DS(on)

Limited by max R

Tj=150°C Tc=25°C

Sinlge pulse

10

AM04908v1

1

10ms

100ms

0.1

0.01

0.1

Figure 4. Output characteristics Figure 5. Transfer characteristics

I

D

(A)

1

VGS=10V

10

200

1s

DS

(V)

V

AM04909v1

6V

(A)

250

I

D

V

DS

=4V

AM04910v1

200

150

100

5V

50

0

Figure 6. Normalized BV

BV

DSS

2

1

4

3

5

DSS

7

6

8

DS

(V)

V

vs temperature Figure 7. Static drain-source on resistance

AM04911v1

(norm)

R

50

0

DS(on)

(Ω)

2

0

4

8

6

10

V

GS

(V)

AM04912v1

7.0

1.10

6.9

6.8

1.05

6.7

6.6

1.00

6.5

6.4

0.95

0.90

-50

T

J

100

150

50

0

(°C)

6.3

6.2

6.1 5

0

10

15

20

I

D

(A)

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STK20N75F3 Electrical characteristics

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations

V

GS

(V)

12

VDD=37.5V

D

=20A

I

10

8

6

4

2

0

10

20

30

40

50

AM04913v1

Q

g

(nC)

C

7000

6000

5000

4000

3000

2000

1000

(pF)

AM04914v1

Ciss

Crss

0

40

0

10

20

30

50

60

70

V

Coss

DS

(V)

Figure 10. Normalized gate threshold voltage

V (norm)

vs temperature

GS(th)

1.2

1.0

0.8

0.6

0.4

-50

AM04915v1

150

T

J

0

50

100

(°C)

Figure 12. Source-drain diode forward

characteristics

V

SD

(V)

0.9

AM04917v1

TJ=-50°C

Figure 11. Normalized on resistance vs

temperature

R

DS(on)

(norm)

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

-50

I

D

=10A

GS

=10V

V

100

150

50

0

AM00895v1

T

J

(°C)

0.8

TJ=25°C

0.7

0.6

TJ=175°C

0.5

0.4 0

5

10

15

20

I

SD

(A)

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Test circuits STK20N75F3

3 Test circuits

Figure 13. Switching times test circuit for

PW

resistive load

VGS

VD

RG

RL

D.U.T.

2200

µF

3.3 µF

AM01468v1

V

DD

Figure 15. Test circuit for inductive load

G

25

Ω

switching and diode recovery times

A

D

D.U. T.

S

B

R

FAST DIODE

G

A

L=100µH

B

D

G

S

3.3

µF

1000

µF

V

DD

Figure 14. Gate charge test circuit

V

i=20V=VGMAX

PW

2200 µF

1kΩ

12V

IG=CONST

2.7kΩ

47kΩ

100Ω

100nF

D.U.T.

AM01469v1

Figure 16. Unclamped inductive load test

circuit

L

VD

ID

Vi

D.U. T.

2200

µF

3.3 µF

1kΩ

VDD

V

VDD

G

Pw

AM01470v1

AM01471v1

Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

V(BR)DSS

VD

IDM

ID

VDD

0

AM01472v1

8/15 Doc ID 14849 Rev 2

0

10%

tdon

ton

90%

toff

tr

tdoff

tf

90%

10%

VDS

90%

V

GS

AM01473v1

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STK20N75F3 Test circuits

Figure 19. Gate charge waveform

Vds

Vgs(th)

Qgs1

Qgs2 Qgd

Id

Vgs

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Package mechanical data STK20N75F3

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

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STK20N75F3 Package mechanical data

Table 8. PolarPAK® (option “L”) mechanical data

mm inch

Ref.

Min. Typ. Max. Min. Typ. Max.

A 0.75 0.80 0.85 0.030 0.031 0.033

A1 0.05 0.002

b1 0.48 0.58 0.68 0.019 0.023 0.027

b2 0.41 0.51 0.61 0.016 0.020 0.024

b3 2.19 2.29 2.39 0.086 0.090 0.094

b4 0.89 1.04 1.19 0.035 0.041 0.047

b5 0.23 0.33 0.43 0.009 0.013 0.017

c 0.20 0.25 0.30 0.008 0.010 0.012

D 6 6.15 6.30 0.236 0.242 0.248

D1 5.74 5.89 6.04 0.226 0.232 0.238

E 5.01 5.16 5.31 0.197 0.203 0.209

E1 4.75 4.90 5.05 0.187 0.193 0.199

H1 0.23 0.009

H2 0.45 0.56 0.018 0.022

H3 0.31 0.41 0.51 0.012 0.016 0.020

H4 0.45 0.56 0.018 0.022

K1 4.22 4.37 4.52 0.166 0.172 0.178

K2 1.08 1.13 1.18 0.043 0.044 0.046

K3 1.37 0.054

K4 0.24 0.009

M1 4.30 4.50 4.70 0.169 0.177 0.185

M2 3.43 3.58 3.73 0.135 0.141 0.147

M3 0.22 0.009

M4 0.05 0.002

P1 0.15 0.20 0.25 0.006 0.008 0.010

T1 3.48 3.64 4.10 0.137 0.143 0.161

T2 0.56 0.76 0.95 0.022 0.030 0.037

T3 1.20 0.047

T4 3.90 0.154

T5 0.18 0.36 0.007 0.014

< 0° 10° 12° 0° 10° 12°

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Package mechanical data STK20N75F3

Figure 20. PolarPAK® (option “L”) drawings

12/15 Doc ID 14849 Rev 2

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STK20N75F3 Package mechanical data

Figure 21. Recommended PAD layout

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Revision history STK20N75F3

5 Revision history

Table 9. Document revision history

Date Revision Changes

01-Jul-2008 1 First release

22-Jun-2009 2 Document status promoted from preliminary data to datasheet.

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STK20N75F3

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Doc ID 14849 Rev 2 15/15