Datasheet STGIPS20K60 Datasheet (ST)

SLLIMM™ (small low-loss intelligent molded module)

IPM, 3-phase inverter - 18 A, 600 V short-circuit rugged IGBT

Features

■ IPM 18 A, 600 V 3-phase IGBT inverter bridge

including control ICs for gate driving and free­wheeling diodes

■ Short-circuit rugged IGBTs

■ V

■ 3.3 V, 5 V, 15 V CMOS/TTL inputs

comparators with hysteresis and pull down /
pull up resistors

■ Undervoltage lockout

■ Internal bootstrap diode

■ Interlocking function

■ Smart shutdown function

■ Comparator for fault protection against over

temperature and overcurrent

■ DBC leading to low thermal resistance

■ Isolation rating of 2500 V

negative temperature coefficient

CE(sat)

rms

/min

STGIPS20K60

SDIP-25L

Applications

■ 3-phase inverters for motor drives

■ Home appliances, such as washing machines,

refrigerators, air conditioners and sewing
machine

Description

This intelligent power module provides a compact,
high performance AC motor drive in a simple,
rugged design. Combining ST proprietary control
ICs with the most advanced short-circuit-rugged
IGBT system technology, this device is ideal for 3­phase inverters in applications such as home
appliances and air conditioners. SLLIMM™ is a
trademark of STMicroelectronics.

Table 1. Device summary

Order code Marking Package Packaging

STGIPS20K60 GIPS20K60 SDIP-25L Tube

November 2011 Doc ID 16098 Rev 5 1/20

www.st.com

20

Contents STGIPS20K60

Contents

1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3

2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/20 Doc ID 16098 Rev 5

STGIPS20K60 Internal block diagram and pin configuration

P

P

P

U

V

1 Internal block diagram and pin configuration

Figure 1. Internal block diagram

Pin 1

OUT U

VBOOT U

LIN-U

HIN-U

VCC

OUT V

VBOOT V

GND

LIN-V

HIN-V

LIN

SD/O D

HIN

VCC

DT

GND

LIN

SD/O D

HIN

VCC

DT

GND

Vboot

HVG

OUT

LVG

CP+

Vboot

HVG

OUT

LVG

CP+

Pin 25

NU

NV

OUT W

VBOOT W

LIN

Vboot

LIN-W

HIN-W

SD/OD

CIN

Pin 16

SD/OD

HIN

VCC

DT

GND

HVG

OUT

LVG

CP+

W

NW

Pin 17

AM05002v1

Doc ID 16098 Rev 5 3/20

Internal block diagram and pin configuration STGIPS20K60

Table 2. Pin description

Pin n° Symbol Description

1OUT

2V

3LIN

4HIN

5V

6OUT

7V

U

bootU

U

U

CC

V

boot V

High-side reference output for U phase

Bootstrap voltage for U phase

Low-side logic input for U phase

High-side logic input for U phase

Low voltage power supply

High-side reference output for V phase

Bootstrap voltage for V phase

8 GND Ground

9LINVLow-side logic input for V phase

10 HIN

11 OUT

12 V

boot W

13 LIN

14 HIN

15 SD

/ OD Shutdown logic input (active low) / open-drain (comparator output)

V

W

W

W

High-side logic input for V phase

High-side reference output for W phase

Bootstrap voltage for W phase

Low-side logic input for W phase

High-side logic input for W phase

16 CIN Comparator input

17 N

W

Negative DC input for W phase

18 W W phase output

19 P Positive DC input

20 N

V

Negative DC input for V phase

21 V V phase output

22 P Positive DC input

23 N

U

Negative DC input for U phase

24 U U phase output

25 P Positive DC input

Figure 2. Pin layout (bottom view)

4/20 Doc ID 16098 Rev 5

STGIPS20K60 Electrical ratings

2 Electrical ratings

2.1 Absolute maximum ratings

Table 3. Inverter part

Symbol Parameter Value Unit

V

V

PN(surge)

V

CES

± I

C

± I

CP

P

TOT

t

scw

1. Applied between HIN

2. Calculated according to the iterative formula:

3. Pulse width limited by max junction temperature

Supply voltage applied between P - NU, NV, N

PN

W

Supply voltage (surge) applied between P - NU,

, N

N

V

W

Each IGBT collector emitter voltage (V

Each IGBT continuous collector current

(2)

(3)

= 25°C

at T

C

Each IGBT pulsed collector current 40 A

(1)

= 0)

IN

450 V

500 V

600 V

18 A

Each IGBT total dissipation at TC = 25°C 52 W

Short circuit withstand time, VCE = 0.5 V
TJ = 125 °C, VCC = V

, LINi and GND for i = U, V, W

i

ICTC()

= 15 V, V

boot

-------------------------------------------------------------------------------------------------------=

R

thj c–

V

(BR)CES

(1)

= 0 ÷ 5 V

IN

T

CE sat()max()Tjmax()ICTC

–

jmax()TC

(),()×

5µs

Table 4. Control part

Symbol Parameter Value Unit

Output voltage applied between

OUT

OUT

U,

OUTW - GND

V,

V

boot

- 21 to V

+ 0.3 V

boot

Low voltage power supply -0.3 to +21 V

Comparator input voltage -0.3 to VCC +0.3 V

Bootstrap voltage applied between
V

- OUTi for i = U, V, W

boot i

Logic input voltage applied between HIN, LIN and

IN

GND

-0.3 to 620 V

-0.3 to 15 V

Open drain voltage -0.3 to 15 V

/dt Allowed output slew rate 50 V/ns

V

dV

V

OUT

V

CC

V

CIN

V

boot

V

SD/OD

OUT

Doc ID 16098 Rev 5 5/20

Electrical ratings STGIPS20K60

Table 5. Total system

Symbol Parameter Value Unit

V

ISO

(1)

T

j

T

C

Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.)

Operating junction temperature -40 to 150 °C

Module case operation temperature -40 to 125 °C

1. The maximum junction temperature rating of the power chips integrated within the SDIP module is 150°C
(@T

≤ 100°C). To ensure safe operation of the SDIP module, the average junction temperature should be

C

limited to T

≤ 125°C (@TC ≤ 100°C)

j(avg)

2.2 Thermal data

Table 6. Thermal data

Symbol Parameter Value Unit

R

thJC

Thermal resistance junction-case single IGBT 2.4 °C/W

Thermal resistance junction-case single diode 5 °C/W

2500 V

6/20 Doc ID 16098 Rev 5

STGIPS20K60 Electrical characteristics

3 Electrical characteristics

TJ = 25 °C unless otherwise specified.

Table 7. Inverter part

Val ue

Symbol Parameter Test conditions

V

CE(sat)

I

CES

V

Collector-emitter
saturation voltage

Collector-cut off current

(1)

(V

= 0 “logic state”)

IN

Diode forward voltage V

F

VCC = V

= 12 A

I

C

V

CC

= 12 A, TJ = 125 °C

I

C

V

CE

(1)

IN

= 15 V, V

boot

= V

= 15 V, V

boot

= 600 V, V

CC

= V

IN

IN

Boot

= 0 “logic state”, IC = 12 A - 3.8 V

Inductive load switching time and energy

Min. Typ. Max.

(1)

= 0 ÷ 5 V,

(1)

= 0 ÷ 5 V,

- 2.2 2.75

-1.8

= 15 V - 150 µA

Unit

V

t

t

c(on)

t

t

c(off)

E

E

1. Applied between HIN

Note: t

Turn-on time

on

Crossover time (on) - 150 -

Turn-off time - 730 -

off

Crossover time (off) - 170 -

Reverse recovery time - 60 -

t

rr

Turn-on switching losses - 290 -

on

Turn-off switching losses - 250 -

off

and t

ON

the switching time of IGBT itself under the internally given gate driving condition.

- 300 -

V

= 300 V,

PN

= V

V

CC

(1)

V

IN

= 15 V,

boot

= 0 ÷ 5 V,
IC = 12 A
(see Figure 3)

, LINi and GND for i = U, V, W. (LIN inputs are active-low).

i

include the propagation delay time of the internal drive. t

OFF

C(ON)

and t

C(OFF)

ns

µJ

are

Doc ID 16098 Rev 5 7/20

Electrical characteristics STGIPS20K60

Figure 3. Switching time test circuit

Figure 4. Switching time definition

100% IC 100% IC

t

rr

VCE

VIN

t

ON

t

C(ON)

VIN(ON)

10% IC 90% IC 10% VCE

(a) turn-on

IC IC

VIN

t

OFF

VIN(OFF)

t

10% VCE 10% IC

(b) turn-off

VCE

C(OFF)

AM09223V1

Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity

must be inverted for turn-on and turn-off.

8/20 Doc ID 16098 Rev 5

STGIPS20K60 Electrical characteristics

3.1 Control part

Table 8. Low voltage power supply (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

cc_hys

V

cc_thONVcc

V

cc_thOFFVcc

I

qccu

I

qcc

Vcc UV hysteresis 1.2 1.5 1.8 V

UV turn ON threshold 11.5 12 12.5 V

UV turn OFF threshold 10 10.5 11 V

Undervoltage quiescent
supply current

Quiescent current

VCC = 10 V
SD/OD = 5 V; LIN = 5 V;

HIN = 0, CIN = 0

= 15 V

V

cc

/OD = 5 V; LIN = 5 V

SD

450 µA

3.5 mA

HIN = 0, CIN = 0

V

ref

Table 9. Bootstrapped voltage (VCC = 15 V)

Internal comparator (CIN)
reference voltage

0.5 0.54 0.58 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

BS_hys

V

BS_thON

V

BS_thOFF

I

QBSU

UV hysteresis 1.2 1.5 1.8 V

BS

V

UV turn ON threshold 10.6 11.5 12.4 V

BS

V

UV turn OFF threshold 9.1 10 10.9 V

BS

V

= 10 V

Undervoltage VBS quiescent
current

BS

/OD = 5 V; LIN and

SD
HIN = 5 V; CIN = 0

70 110 µA

I

QBS

R

DS(on)

Table 10. Logic inputs (VCC = 15 V)

VBS quiescent current

Bootstrap driver on resistance LVG ON 120 Ω

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

Low logic level voltage 0.8 V

il

V

I

HINh

I

HINl

I

LINl

I

LINh

I

SDh

I

SDl

High logic level voltage 2.25 V

ih

HIN logic “1” input bias current HIN = 15 V 110 175 260 µA

HIN logic “0” input bias current HIN = 0 V 1 µA

LIN logic “1” input bias current LIN = 0 V 3 6 20 µA

LIN logic “0” input bias current LIN = 15 V 1 µA

SD logic “0” input bias current SD = 15 V 30 120 300 µA

SD logic “1” input bias current SD = 0 V 3 µA

Dt Dead time see Figure 7 600 ns

= 15 V

V

BS

SD/OD = 5 V; LIN and

150 210 µA

HIN = 5 V; CIN = 0

Doc ID 16098 Rev 5 9/20

Electrical characteristics STGIPS20K60

Table 11. Sense comparator characteristics (V

= 15 V)

CC

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

ib

V

t

d_comp

Input bias current V

Open-drain low-level output

ol

voltage

Comparator delay

SR Slew rate C

t

sd

Shut down to high / low side
driver propagation delay

Comparator triggering to high /

t

isd

low side driver turn-off
propagation delay

= 1 V - 3 µA

CP+

= - 3 mA - 0.5 V

I

od

/OD pulled to 5 V through

SD
100 kΩ resistor

= 180 pF; Rpu = 5 kΩ - 60 V/µsec

L

V

= 0, V

OUT

V

= 0 to 3.3 V

IN

boot

= VCC,

- 90 130 ns

50 125 200

Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN

i

50 200 250

Table 12. Truth table

Condition

Shutdown enable
half-bridge tri-state

Interlocking
half-bridge tri-state

0 ‘’logic state”
half-bridge tri-state

1 “logic state”
low side direct driving

1 “logic state”
high side direct driving

Logic input (V

SD

/OD LIN HIN LVG HVG

LXXLL

HLHLL

HHL L L

HLLHL

HHHLH

)Output

I

ns

Note: X: don’t care

10/20 Doc ID 16098 Rev 5

STGIPS20K60 Electrical characteristics

Figure 5. Maximum I

26

26

24

24

22

22

20

20

[A]

[A]

)

)

18

18

c(RMS

c(RMS

I

I

16

16

14

14

12

12

10

10

switching frequency

TC= 100 °C

TC= 100 °C

VPN= 300 V, Modulation index = 0.8,

VPN= 300 V, Modulation index = 0.8,

= 0.6, Tj= 150 °C, f

= 0.6, Tj= 150 °C, f

P

P

F

F

4 8 12 16 20

4 8 12 16 20

C(RMS)

TC= 80 °C

TC= 80 °C

= 60 Hz

= 60 Hz

SINE

SINE

current vs.

(1)

fSW[kHz]

fSW[kHz]

Figure 6. Maximum I

AM07841v1

1. Simulated curves refer to typical IGBT parameters and maximum R

current vs. f

(1)

16

16

15

15

VPN= 300 V, Modulation index = 0.8,

VPN= 300 V, Modulation index = 0.8,

14

14

= 0.6, Tj = 150 °C, TC= 100 °C

= 0.6, Tj = 150 °C, TC= 100 °C

P

P

F

F

13

13

[A]

[A]

12

12

c(RMS)

c(RMS)

I

I

11

11

fSW= 12 kHz

10

10

9

9

8

8

110100

110100

fSW= 12 kHz

fSW= 16 kHz

fSW= 16 kHz

fSW= 20 kHz

fSW= 20 kHz

C(RMS)

f

f

SINE

SINE

SINE

AM07842v1

[Hz]

[Hz]

thj-c.

Doc ID 16098 Rev 5 11/20

Electrical characteristics STGIPS20K60

3.2 Waveforms definitions

Figure 7. Dead time and interlocking waveforms definitions

LIN

CONTROL SIGNAL EDGES
OVERLAPPED:

INTERLOCKING + DEAD TIME

CONTROL SIGNALS EDGES
SYNCHRONOUS (*):

DEAD TIME

CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:

DEAD TIME

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

INTERLOCKING

DTLH

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTLH DTHL

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LH

DT

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

INTERLOCKING

DTHL

DT

HL

CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:

DIRECT DRIVING

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTLH

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTHL

(*) HIN and LIN can be connected together and driven by just one control signal

LIN

12/20 Doc ID 16098 Rev 5

STGIPS20K60 Smart shutdown function

4 Smart shutdown function

The STGIPS20K60 integrates a comparator for fault sensing purposes. The comparator
non-inverting input (CIN) can be connected to an external shunt resistor in order to
implement a simple over-current protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the half­bridge in tri-state. In the common overcurrent protection architectures the comparator output
is usually connected to the shutdown input through a RC network, in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
internal logic turns on the open-drain output and holds it on until the shutdown voltage goes
below the logic input lower threshold. Finally the smart shutdown function provides the
possibility to increase the real disable time without increasing the constant time of the
external RC network.

Figure 8. Smart shutdown timing waveforms

comp

Vref

CP+

HIN/LIN

HVG/LVG

SD/OD

upper

threshold

lower

threshold

1

open drain gate

(internal)

the driver outputs are set in SD state

immediately after the comparator

triggering even if the SD signal

Fast shut down:

has not yet reach

the lower input threshold

PROTECTION

real disable time

TIME CONSTANTS

= (RON_OD // RSD) CSD

1

= RSD CSD

2

2

SHUT DOWN CIRCUIT

V

BIAS

FROM/TO

CONTROLLER

RSD

CSD

SD/OD

RON_OD

SMART

SD

LOGIC

Pls refer to Table 11 for internal propagation delay time details.

Doc ID 16098 Rev 5 13/20

Applications information STGIPS20K60

2

+

5 Applications information

Figure 9. Typical application circuit

VDC

M

Rshunt

P

U

D1

Nu

D2

V

D3

Nv

D4

W

D5

Nw

D6

R

C

T1

Rg

Vboot

LIN

VBOOT U

OUT U

LIN-U

T2

Rg

LVG

OUT

HVG

SD/OD

HIN

HIN-U

CP+

VCC

GND

DT

Cdt

Rdt

Cvcc

VCC

T3

Rg

Vboot

LIN

GND

VBOOT V

OUT V

T4

Rg

LVG

HIN-V

CP+

VCC

GND

DT

Rdt Cdt

Cvcc

OUT

HVG

SD/OD

HIN

LIN-V

T5

Rg

Vboot

LIN

VBOOT W

OUT W

T6

Rg

LVG

OUT

HVG

SD/OD

HIN

HIN-W

LIN-W

CP+

VCC

DT

Cvcc

SD/OD

GND

Cdt

Rdt

CIN

Cbu

VCC

Cbv

CONTROLLER

14/20 Doc ID 16098 Rev 5

Cbw

Rsd

Csd

3.3V/5V Line

AM05001v

STGIPS20K60 Applications information

5.1 Recommendations

● Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each

high side input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.

● Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an

internal 5 V regulator through a diode, is built-in for each low side input.

● To prevent the input signals oscillation, the wiring of each input should be as short as

possible.

● By integrating an application specific type HVIC inside the module, direct coupling to

MCU terminals without any opto-coupler is possible.

● Each capacitor should be located as nearby the pins of IPM as possible.

● Low inductance shunt resistors should be used for phase leg current sensing.

● Electrolytic bus capacitors should be mounted as close to the module bus terminals as

possible. Additional high frequency ceramic capacitor mounted close to the module
pins will further improve performance.

● The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see

Section 4: Smart shutdown function for detailed info).

Table 13. Recommended operating conditions

Symbol Parameter Conditions

V

V

V

t

dead

f

PWM

PN

CC

BS

Supply Voltage Applied between P-Nu,Nv,Nw 300 400 V

Control supply voltage Applied between VCC-GND 13.5 15 18 V

High side bias voltage

Blanking time to

prevent Arm-short

PWM input signal

Applied between V
i=U,V,W

For each input signal 1 µs

-40°C < T

< 100°C

c

-40°C < Tj < 125°C

BOOTi

-OUTi for

Val ue

Unit

Min. Typ. Max.

13 18 V

20 kHz

Doc ID 16098 Rev 5 15/20

Package mechanical data STGIPS20K60

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Please refer to dedicated technical note TN0107 for mounting instructions.

Table 14. SDIP-25L mechanical data

(mm.)

Dim.

Min. Typ. Max.

A 43.90 44.40 44.90

A1 1.15 1.35 1.55

A2 1.40 1.60 1.80

A3 38.90 39.40 39.90

B 21.50 22.00 22.50

B1 11.25 11.85 12.45

B2 24.70 25.20 25.70

C 5.00 5.40 6.00

C1 6.50 7.00 7.50

C2 11.20 11.70 12.20

e 2.15 2.35 2.55

e1 3.40 3.60 3.80

e2 4.50 4.70 4.90

e3 6.30 6.50 6.70

D33.30

D1 5.55

E11.20

E1 1.40

F 0.85 1.00 1.15

F1 0.35 0.50 0.65

R 1.55 1.75 1.95

T 0.45 0.55 0.65

V0° 6°

16/20 Doc ID 16098 Rev 5

STGIPS20K60 Package mechanical data

Figure 10. SDIP-25L package dimensions

8154676_G

Doc ID 16098 Rev 5 17/20

Package mechanical data STGIPS20K60

Figure 11. Packaging specifications of SDIP-25L package

18/20 Doc ID 16098 Rev 5

STGIPS20K60 Revision history

7 Revision history

Table 15. Document revision history

Date Revision Changes

10-Aug-2009 1 Initial release

Document status promoted from preliminary to datasheet.

01-Jul-2010 2

Updated package mechanical data (Section 6: Package

mechanical data).

Minor text changes to improve readability.

23-Sep-2010 3

03-May-2011 4

04-Nov-2011 5

Updated: Ta bl e 3 , 5, 10 and Tabl e 1 1. Modified: Figure 5 and

Figure 6.

Updated title with SLLIMM™ in cover page, added SDIP-25L
tube dimensions Figure 11 on page 18.

Updated title with SLLIMM™ (small low-loss intelligent molded
module) IPM, 3-phase inverter - 18 A, 600 V short-circuit
rugged IGBT in cover page and SDIP-25L mechanical data

Table 14 on page 16, Figure 10 on page 17.

Doc ID 16098 Rev 5 19/20

STGIPS20K60

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20/20 Doc ID 16098 Rev 5