Datasheet STGIPL14K60 Datasheet (ST)

SLLIMM™ (small low-loss intelligent molded module)

IPM, 3-phase inverter - 15 A, 600 V short-circuit rugged IGBT

Features

■ IPM 15 A, 600 V 3-phase IGBT inverter bridge

including control ICs for gate driving and free­wheeling diodes

■ Short-circuit rugged IGBTs

■ V

■ 3.3 V, 5 V, 15 V CMOS/TTL inputs

comparators with hysteresis and pull down/pull
up resistors

■ Undervoltage lockout

■ Internal bootstrap diode

■ Interlocking function

■ Smart shut down function

■ Comparator for fault protection against

overtemperature and overcurrent

■ Op amps for advanced current sensing

■ DBC substrate leading to low thermal

resistance

■ Isolation rating of 2500 V

■ 5 kΩ NTC for temperature control

Applications

negative temperature coefficient

CE(sat)

rms

/min

STGIPL14K60

SDIP-38L

AM01193v1

Description

This intelligent power module provides a compact,
high performance AC motor drive in a simple,
rugged design. Combining ST proprietary control
ICs with the most advanced short-circuit-rugged
IGBT system technology, this device is ideal for 3­phase inverters in applications such as home
appliances and air conditioners. SLLIMM™ is a
trademark of STMicroelectronics.

■ 3-phase inverters for motor drives

■ Home appliances, such as washing machines,

refrigerators, air conditioners and sewing
machines

Table 1. Device summary

Order code Marking Package Packaging

STGIPL14K60 GIPL14K60 SDIP-38L Tube

November 2011 Doc ID 15589 Rev 6 1/22

www.st.com

22

Contents STGIPL14K60

Contents

1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3

2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22 Doc ID 15589 Rev 6

STGIPL14K60 Internal block diagram and pin configuration

1 Internal block diagram and pin configuration

Figure 1. Internal block diagram

Doc ID 15589 Rev 6 3/22

Internal block diagram and pin configuration STGIPL14K60

Table 2. Pin description

Pin Symbol Description

1OUT

2V

3LIN

4HIN

5OP-

6OP

boot U

U

U

U

OUT U

7OP+

8CIN

U

9OUT

10 V

11 LIN

12 HIN

13 OP-

14 OP

boot V

V

V

V

OUT V

15 OP+

16 CIN

17 OUT

18 V

19 LIN

20 HIN

21 OP-

22 OP

23 OP+

24 CIN

25 V

26 SD

V

W

boot W

W

W

W

OUT W

W

W

CC

/ OD Shut down logic input (active low) / open drain (comparator output)

High side reference output for U phase

U

Bootstrap voltage for U phase

Low side logic input for U phase

High side logic input for U phase

Op amp inverting input for U phase

Op amp output for U phase

Op amp non inverting input for U phase

U

Comparator input for U phase

High side reference output for V phase

V

Bootstrap voltage for V phase

Low side logic input for V phase

High side logic input for V phase

Op amp inverting input for V phase

Op amp output for V phase

Op amp non inverting input for V phase

V

Comparator input for V phase

High side reference output for W phase

Bootstrap voltage for W phase

Low side logic input for W phase

High side logic input for W phase

Op amp inverting input for W phase

Op amp output for W phase

Op amp non inverting input for W phase

Comparator input for W phase

Low voltage power supply

27 GND Ground

28 T

29 T

30 N

2

1

W

NTC thermistor terminal 2

NTC thermistor terminal 1

Negative DC input for W phase

31 W W phase output

32 P Positive DC input

33 N

V

Negative DC input for V phase

34 V V phase output

4/22 Doc ID 15589 Rev 6

STGIPL14K60 Internal block diagram and pin configuration

Table 2. Pin description (continued)

Pin Symbol Description

35 P Positive DC input

36 N

U

Negative DC input for U phase

37 U U phase output

38 P Positive DC input

Figure 2. Pin layout (bottom view)

Marking area

Doc ID 15589 Rev 6 5/22

Electrical ratings STGIPL14K60

2 Electrical ratings

2.1 Absolute maximum ratings

Table 3. Inverter part

Symbol Parameter Value Unit

V

V

PN(surge)

V

CES

± I

± I

CP

P

TOT

t

scw

1. Applied between HINi, LINi and GND for i = U, V, W

2. Calculated according to the iterative formula:

3. Pulse width limited by max junction temperature

Supply voltage applied between P-NU, NV, N

PN

Supply voltage (surge) applied between P-NU, NV,
N

W

Each IGBT collector emitter voltage (V

Each IGBT continuous collector current

(2)

C

(3)

= 25°C

at T

C

Each IGBT pulsed collector current 30 A

Each IGBT total dissipation at TC = 25°C

Short circuit withstand time, VCE = 0.5 V

= 125 °C, VCC = V

T

j

ICTC()

= 15 V, V

boot

-------------------------------------------------------------------------------------------------------=

R

thj c–

IN

V

CE sat()max()Tjmax()ICTC

Table 4. Control part

(1)

IN

(BR)CES

(1)

= 0÷5 V

T

jmax()TC

W

= 0)

–

450 V

500 V

600 V

15 A

44 W

5µs

(),()×

Symbol Parameter Value Unit

V

OUT

V

V

CIN

V

boot

V

V

SD/OD

dV

out

Output voltage applied between OUTU, OUTV,

- GND (VCC = 15 V)

OUT

W

Low voltage power supply -0.3 to +21 V

CC

Comparator input voltage

Bootstrap voltage applied between V
for i = U, V, W

Logic input voltage applied between HIN, LIN and

IN

GND

Open drain voltage -0.3 to 15 V

/dt

Allowed output slew rate 50 V/ns

6/22 Doc ID 15589 Rev 6

boot i

- OUTi

V

- 21 to V

boot

-0.3 to V

CC

boot

+0.3

-0,3 to 620 V

-0.3 to 15 V

+ 0.3

V

V

STGIPL14K60 Electrical ratings

Table 5. Total system

Symbol Parameter Value Unit

V

ISO

(1)

T

j

T

C

Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60sec.)

Operating junction temperature -40 to 150 °C

Module case operation temperature -40 to 125 °C

1. The maximum junction temperature rating of the power chips integrated within the SDIP module is 150°C
(@T

≤ 100°C). To ensure safe operation of the SDIP module, the average junction temperature should be

C

limited to T

≤ 125°C (@TC ≤ 100°C)

j(avg)

2.2 Thermal data

Table 6. Thermal data

Symbol Parameter Value Unit

R

th(j-c)

Thermal resistance junction-case single IGBT 2.8 °C/W

Thermal resistance junction-case single diode 5 °C/W

2500 V

Doc ID 15589 Rev 6 7/22

Electrical characteristics STGIPL14K60

3 Electrical characteristics

Tj = 25 °C unless otherwise specified.

Table 7. Inverter part

Symbol Parameter Test condition

V

CE(sat)

I

CES

V

F

Inductive load switching time and energy

Collector-emitter
saturation voltage

Collector-cut off current

(1)

=0 “logic state”)

(V

IN

Diode forward voltage V

Val ue

Min. Typ. Max.

VCC = V

= 7 A

I

C

= V

V

CC

= 7 A, Tj= 125 °C

I

C

V

CE

V

CC

(1)

IN

= 15 V, V

Boot

= 15 V, V

Boot

= 600 V
= V

= 15 V

boot

= 0 “logic state”, IC = 7 A - 2.1 V

(1)

IN

(1)

IN

= 0 ÷ 5 V,

= 0 ÷ 5 V,

-2.12.5

-1.8

- 150 µA

Unit

V

t

t

c(on)

t

t

c(off)

E

E

1. Applied between HINi LINi and GND for i = U, V, W (LIN inputs are active-low).

Note: ton and t

Turn-on time

on

Crossover time (on) - 130

= 300 V,

V

Turn-off time - 320

off

Crossover time (off) - 110

t

Reverse recovery time - 130

rr

Turn-on switching losses - 150

on

Turn-off switching losses - 90

off

include the propagation delay time of the internal drive. t

off

DD

= V

V

CC

V

IN

= 7 A

I

C

(1)

= 15 V,

boot

= 0 ÷ 5 V,

(see Figure 3)

switching time of IGBT itself under the internally given gate driving condition.

- 270

C(ON)

and t

C(OFF)

ns

µJ

are the

8/22 Doc ID 15589 Rev 6

STGIPL14K60 Electrical characteristics

Figure 3. Switching time test circuit

Figure 4. Switching time definition

100% IC 100% IC

t

rr

VCE

IC IC

VIN

t

ON

t

C(ON)

VIN(ON)

10% IC 90% IC 10% VCE

VIN

VIN(OFF)

t

OFF

VCE

t

C(OFF)

10% VCE 10% IC

(a) turn-on

(b) turn-off

AM09223V1

Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity

must be inverted for turn-on and turn-off.

Doc ID 15589 Rev 6 9/22

Electrical characteristics STGIPL14K60

3.1 Control part

Table 8. Low voltage power supply (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

cc_hys

V

cc_thON

V

cc_thOFFVcc

I

qccu

I

qcc

Vcc UV hysteresis 1.2 1.5 1.8 V

Vcc UV turn ON threshold 11.5 12 12.5 V

UV turn OFF threshold 10 10.5 11 V

Undervoltage quiescent
supply current

Quiescent current

VCC = 10 V

/OD = 5 V; LIN = 5 V;

SD
HIN = 0, CIN = 0

= 15 V

V

cc

/OD = 5 V; LIN = 5 V

SD

450 µA

3.5 mA

HIN = 0, CIN = 0

V

ref

Table 9. Bootstrapped voltage (VCC = 15 V)

Internal comparator (CIN)
reference voltage

0.5 0.54 0.58 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

BS_hys

V

BS_thON

V

BS_thOFF

I

QBSU

I

QBS

V

UV hysteresis 1.2 1.5 1.8 V

BS

V

UV turn ON threshold 10.6 11.5 12.4 V

BS

V

UV turn OFF threshold 9.1 10 10.9 V

BS

Undervoltage VBS quiescent
current

VBS quiescent current

VBS = 10 V
SD/OD = 5 V; LIN and

HIN = 5 V; CIN = 0

= 15 V

V

BS

/OD = 5 V; LIN and

SD

70 110 µA

150 210 µA

HIN = 5 V; CIN = 0

R

DS(on)

Table 10. Logic inputs (VCC = 15 V)

Bootstrap driver on resistance LVG ON 120 Ω

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

Low logic level voltage 0.8 V

il

V

I

HINh

I

HINl

I

LINl

I

LINh

I

SDh

I

SDl

High logic level voltage 2.25 V

ih

HIN logic “1” input bias current HIN = 15 V 110 175 260 µA

HIN logic “0” input bias current HIN = 0 V 1 µA

LIN logic “1” input bias current LIN = 0 V 3 6 20 µA

LIN logic “0” input bias current LIN = 15 V 1 µA

SD logic “0” input bias current SD = 15 V 30 120 300 µA

SD logic “1” input bias current SD = 0 V 3 µA

Dt Dead time see Figure 8 600 ns

10/22 Doc ID 15589 Rev 6

STGIPL14K60 Electrical characteristics

Table 11. OPAMP characteristics (VCC = 15 V)

Symbol Parameter Test condition Min. Typ. Max. Unit

V

I

io

I

ib

V

icm

V

OL

V

OH

I

o

SR Slew rate

GBWP Gain bandwidth product V

A

vd

SVR Supply voltage rejection ratio vs. V

Input offset voltage Vic = 0 V, Vo = 7.5 V 6 mV

io

Input offset current

Input bias current

(1)

Vic = 0 V, Vo = 7.5 V

Input common mode voltage
range

Low level output voltage RL = 10 kΩ to V

0V

CC

440nA

100 200 nA

75 150 mV

High level output voltage RL = 10 kΩ to GND 14 14.7 V

Output short circuit current

Source,
V

= +1; Vo = 0 V

id

Sink,

= -1; Vo = V

V

id

V

= 1 ÷ 4 V; C

i

CC

= 100 pF;

L

unity gain

= 7.5 V 8 12 MHz

o

16 30 mA

50 80 mA

2.5 3.8 V/μs

Large signal voltage gain RL = 2 kΩ 70 85 dB

CC

60 75 dB

CMRR Common mode rejection ratio 55 70 dB

1. The direction of input current is out of the IC.

Table 12. Sense comparator characteristics (VCC = 15 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

ib

V

t

d_comp

SR Slew rate C

t

sd

t

isd

Input bias current V

Open-drain low-level output

ol

voltage

Comparator delay

Shut down to high / low side
driver propagation delay

Comparator triggering to high /
low side driver turn-off
propagation delay

= 1 V - 3 µA

CP+

= - 3 mA - 0.5 V

I

od

/OD pulled to 5 V through

SD
100 kΩ resistor

= 180 pF; Rpu = 5 kΩ - 60 V/µsec

L

V

= 0, V

OUT

V

= 0 to 3.3 V

IN

Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN

i

boot

= VCC,

- 90 130 ns

50 125 200

ns

50 200 250

Doc ID 15589 Rev 6 11/22

Electrical characteristics STGIPL14K60

Table 13. Truth table

Logic input (V

Condition

SD

/OD LIN HIN LVG HVG

Shutdown enable
half-bridge 3-state

Interlocking
half-bridge 3-state

0 ‘’logic state”
half-bridge 3-state

1 “logic state”
low side direct driving

1 “logic state”
high side direct driving

LXXLL

HLHLL

HHL L L

HLLHL

HHHLH

Note: X: don’t care.

Figure 5. Maximum I

20

switching frequency

C(RMS)

current vs.

(1)

AM07839v1

)Output

I

Figure 6. Maximum I

12

12

C(RMS)

current vs. f

sine

AM07840v1

(1)

18

16

[A]

14

c(RMS)

I

12

10

8

468 10 12 14 16 18 20

VPN= 300 V, Modulation index = 0.8,

P

= 0.6, Tj= 150 °C, f

F

TC= 100 °C

SINE

TC= 80 °C

= 60 Hz

fSW[kHz]

1. Simulated curves refer to typical IGBT parameters and maximum R

11

11

VPN= 300 V, Modulation index = 0.8,

VPN= 300 V, Modulation index = 0.8,

= 0.6, Tj= 150 °C, TC= 10 °C

= 0.6, Tj= 150 °C, TC= 10 °C

P

P

F

F

10

10

[A]

[A]

9

9

c(RMS)

c(RMS)

I

I

8

8

7

7

6

6

1 10 100

1 10 100

fSW= 12 kHz

fSW= 12 kHz

fSW= 16 kHz

fSW= 16 kHz

fSW= 20 kHz

fSW= 20 kHz

f

f

SINE

SINE

thj-c.

[Hz]

[Hz]

12/22 Doc ID 15589 Rev 6

STGIPL14K60 Electrical characteristics

3.1.1 NTC thermistor

Table 14. NTC thermistor

Symbol Parameter Test conditions Min. Typ. Max. Unit.

R

25

R

125

B B-constant T

Resistance TC = 25°C 5 kΩ

Resistance TC = 125°C 300 Ω

= 25°C 3435 K

C

T Operating temperature -40 125 °C

Equation 1: resistance variation vs. temperature

1

1

⎛⎞

B

---

--------- -–

⎝⎠

T

RT() R25e

⋅=

298

Where T are temperatures in Kelvins

Figure 7. NTC resistance vs. temperature

Doc ID 15589 Rev 6 13/22

Electrical characteristics STGIPL14K60

3.2 Waveforms definitions

Figure 8. Dead time and interlocking waveforms definitions

LIN

CONTROL SIGNAL EDGES
OVERLAPPED:

INTERLOCKING + DEAD TIME

CONTROL SIGNALS EDGES
SYNCHRONOUS (*):

DEAD TIME

CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:

DEAD TIME

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LIN

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

INTERLOCKING

DTLH

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTLH DTHL

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

LH

DT

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

INTERLOCKING

DTHL

DT

HL

CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:

DIRECT DRIVING

HIN

LVG

HVG

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTLH

gate driver outputs OFF

(HALF-BRIDGE TRI-STATE)

DTHL

(*) HIN and LIN can be connected together and driven by just one control signal

LIN

14/22 Doc ID 15589 Rev 6

STGIPL14K60 Smart shutdown function

4 Smart shutdown function

The STGIPL14K60 integrates a comparator for fault sensing purposes. The comparator
non-inverting input (CIN) can be connected to an external shunt resistor in order to
implement a simple over-current protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the half­bridge in 3-state. In the common overcurrent protection architectures the comparator output
is usually connected to the shutdown input through a RC network, in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
internal logic turns on the open-drain output and holds it on until the shutdown voltage goes
below the logic input lower threshold. Finally the smart shutdown function provides the
possibility to increase the real disable time without increasing the constant time of the
external RC network.

Figure 9. Smart shutdown timing waveforms

comp

Vref

CP+

PROTECTION

HIN/LIN

HVG/LVG

SD/OD

upper

threshold

lower

threshold

1

2

open drain gate

(internal)

Fast shut down:

real disable time

the driver outputs are set in SD state

immediately after the comparator

triggering even if the SD signal

has not yet reach

TIME CONSTANTS

= (RON_OD // RSD) CSD

1

= RSD CSD

2

the lower input threshold

SHUT DOWN CIRCUIT

V

BIAS

FROM/TO

CONTROLLER

RSD

CSD

SD/OD

RON_OD

SMART

SD

LOGIC

Pls refer to Table 12 for internal propagation delay time details.

Doc ID 15589 Rev 6 15/22

Applications information STGIPL14K60

5 Applications information

Figure 10. Typical application circuit

16/22 Doc ID 15589 Rev 6

STGIPL14K60 Applications information

5.1 Recommendations

● Input signal HIN is active high logic. A 85kΩ (typ.) pull down resistor is built-in for each

high side input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.

● Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an

internal 5 V regulator through a diode, is built-in for each low side input.

● To prevent the input signals oscillation, the wiring of each input should be as short as

possible.

● By integrating an application specific type HVIC inside the module, direct coupling to

MCU terminals without any opto-coupler is possible.

● Each capacitor should be located as nearby the pins of IPM as possible.

● Low inductance shunt resistors should be used for phase leg current sensing.

● Electrolytic bus capacitors should be mounted as close to the module bus terminals as

possible. Additional high frequency ceramic capacitor mounted close to the module
pins will further improve performance.

● The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see

Section 4: Smart shutdown function for detailed info).

Table 15. Recommended operating conditions

Symbol Parameter Conditions

V

V

V

t

dead

f

PWM

PN

CC

BS

Supply Voltage Applied between P-Nu, Nv, Nw 300 400 V

Control supply voltage Applied between VCC-GND 13.5 15 18 V

High side bias voltage

Blanking time to

prevent Arm-short

PWM input signal

Applied between V
i = U, V, W

For each input signal 1 µs

-40°C < T

< 100°C

c

-40°C < Tj < 125°C

BOOTi

-OUTi for

Val ue

Unit

Min. Typ. Max.

13 18 V

20 kHz

Doc ID 15589 Rev 6 17/22

Package mechanical data STGIPL14K60

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

Please refer to dedicated technical note TN0107 for mounting instructions.

Table 16. SDIP-38L mechanical data

mm.

Dimensions

Min. Typ. Max.

A 49.10 49.60 50.10

A1 1.10 1.30 1.50

A2 1.40 1.60 1.80

A3 44.10 44.60 45.10

B 24.00 24.50 25.00

B1 11.25 11.85 12.45

B2 27.10 27.60 28.10

B3 28.60 29.10 29.60

C 5.00 5.40 6.00

C1 6.50 7.00 7.50

C2 10.35 10.85 11.35

e 1.10 1.30 1.50

e1 3.20 3.40 3.60

e2 5.80 6.00 6.20

e3 4.60 4.80 5.00

e4 5.60 5.80 6.00

e5 6.30 6.50 6.70

e6 4.50 4.70 4.90

D38.10

D1 5.75

E11.80

E1 2.15

F 0.85 1.00 1.15

F1 0.35 0.50 0.65

R 1.55 1.75 1.95

T 0.45 0.55 0.65

V0° 6°

18/22 Doc ID 15589 Rev 6

STGIPL14K60 Package mechanical data

Figure 11. SDIP-38L drawing dimensions

8142868_G

Doc ID 15589 Rev 6 19/22

Package mechanical data STGIPL14K60

Figure 12. SDIP-38L tube dimensions

20/22 Doc ID 15589 Rev 6

8304140_A

STGIPL14K60 Revision history

7 Revision history

Table 17. Document revision history

Date Revision Changes

16-Apr-2009 1 Initial release

Inserted Figure 5, Figure 6 and Section 4: Smart shutdown function.

29-Mar-2010 2

14-Jun-2010 3

21-Sep-2010 4

09-Mar-2011 5

04-Nov-2011 6

Updated Section 3.1: Control part and package mechanical data,

Section 6.

Minor text changes to improve readability.

Document status promoted from preliminary data to datasheet.
Updated Table 7: Inverter part, Figure 5: Maximum IC(RMS) current

vs. switching frequency and Figure 6: Maximum IC(RMS) current
vs. fsine(1).

Updated: Ta b le 3 , 5, 8, 9, 10 and 12.
Modified: Figure 5 and Figure 6.

Updated title with SLLIMM™ in cover page, added SDIP-38L tube
dimensions Figure 12 on page 20.

Updated title with SLLIMM™ (small low-loss intelligent molded
module) IPM, 3-phase inverter - 15 A, 600 V short-circuit rugged
IGBT in cover page and SDIP-38L mechanical data Table 16 on

page 18, Figure 11 on page 19.

Doc ID 15589 Rev 6 21/22

STGIPL14K60

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