Datasheet STG5678 Datasheet (ST)

Page 1
Features
■ Distortion-free negative signal throughput
down to V
■ Wide operating voltage range:
V
(opr) = 1.65 to 4.5 V single supply
■ Ultra low power dissipation:
I
= 0.2 µA (max.) at TA = 85 °C
CC
■ Low ON resistance:
R
= 0.5 Ω (max. TA = 25 °C) at VCC = 3.6 V
ON
■ 4.3 V tolerant and 1.8 V compatible threshold
on digital control input at V
■ Latch-up performance exceeds 300 mA
(JESD 17)
■ ESD performance:
– 2000-V human-body model
(IEC61340-3-1:2002 level 2)
– 200-V machine model
(IEC61340-3-2 level M2)
– 1000-V charge device model
(JESD22-C101-A level III)
- 5.5 V
= 1.65 V to 4.5 V
CC
STG5678
Low voltage dual SPDT switch
with negative rail capability
Flip-chip 12
Description
The STG5678 is a high-speed CMOS low voltage dual analog SPDT (single pole dual throw) switch or 2:1 multiplexer/de-multiplexer switch fabricated in silicon gate CMOS technology. It is designed to operate from 1.65 to 4.5 V.
The device is capable of handling signals with negative voltages from V any distortion.
- 5.5 V to VCC without
Additional key features are fast switching speed, break-before-make delay time and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.

Table 1. Device summary

Order code Package Packaging
STG5678BJR Flip-chip 12 Tape and reel
STG5678CJR Flip-chip 12 (with back side coating) Tape and reel
June 2010 Doc ID 14580 Rev 3 1/23
www.st.com
23
Page 2
Contents STG5678
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 STG5678 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Application hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Input signal dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23 Doc ID 14580 Rev 3
Page 3
STG5678 Pin settings

1 Pin settings

1.1 Pin connection

Figure 1. Pin connection (bump side view)

See note 1
1. Note 1: bump A1 is distinguished by a circular dot on the top-side. There is no circular dot on the bump­side.
A B C D
A1
A2
2
A3

1.2 Pin description

Table 2. Pin assignment

Pin number Symbol Name and function
B1
B2
B3
C1
C2
C3
D1
D2
D3
A B C D
1SEL
NC
2
2SEL
1S1
GND
2S1
D1
GND
D2
1S2
V
2S2
CC
A1 1SEL Selection control for switch 1
A2 NC No connection
A3 2SEL Selection control for switch 2
B1 1S1 Independent channel for switch 1
B2 GND Ground (0 V)
B3 2S1 Independent channel for switch 2
C1 D1 Common channel for switch 1
C2 GND Ground (0 V)
C3 D2 Common channel for switch 2
D1 1S2 Independent channel for switch 1
D2
V
CC
Positive supply voltage
D3 2S2 Independent channel for switch 2
Doc ID 14580 Rev 3 3/23
Page 4
STG5678 device summary STG5678

2 STG5678 device summary

Figure 2. Functional diagram

D2
D2
D1
D1

Figure 3. Input equivalent circuit

D
2SEL
2SEL
1SEL
1SEL
2S1
2S1
2S2
2S2
1S1
1S1
1S2
1S2
S2
SEL

Table 3. Truth table

SEL Switch S1 Switch S2
HONOFF
LOFF
1. High impedance
4/23 Doc ID 14580 Rev 3
(1)
S1
(1)
ON
Page 5
STG5678 Maximum rating

3 Maximum rating

Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit
V
V
V
I
I
I
I
CC
I
GND
P
T
1. Derate above 70 ºC by 18.5 mW/C
Supply voltage -0.5 to 5.5 V
CC
V
DC input voltage
I
DC control input voltage -0.5 to 5.5 V
IC
DC output voltage
O
DC input diode current on control pin (V
IKC
DC input diode current (VIN<0V) ±50 mA
I
IK
DC output diode current ±20 mA
OK
DC output current ±150 mA
I
O
DC output current peak (pulse at 1ms, 10% duty cycle) ±400 mA
OP
or
DC VCC or ground current ±100 mA
Power dissipation at TA = 70°C
D
Storage temperature -65 to 150 °C
stg
Lead temperature (10 sec) 300 °C
T
L
(1)
- 6.0) to
- (V
CC
VCC + 0.5
- 6.0 V) to
- (V
CC
+ 0.5
V
CC
<0V) -50 mA
SEL
1120 mW
V
V
Doc ID 14580 Rev 3 5/23
Page 6
Maximum rating STG5678

3.1 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Value Unit
V
CC
V
I
V
IC
V
O
T
op
dt/dv
Supply voltage 1.65 to 4.5 V
Input voltage VCC -5.5 to V
CC
V
Control input voltage 0 to 4.5 V
Output voltage VCC -5.5 to V
CC
V
Operating temperature -40 to 85 °C
= 1.65 to 2.7 V 0 to 20
V
Input rise and fall time control input
CC
= 3.0 to 4.5 V 0 to 10
V
CC
ns/V
6/23 Doc ID 14580 Rev 3
Page 7
STG5678 Electrical characteristics

4 Electrical characteristics

Table 6. DC specifications

Test conditions Value
Symbol Parameter
V
CC
(V)
1.65
−1.95 0.9 – – 0.9 –
2.25
V
IH
High level input voltage
−2.7 0.9 – – 0.9 –
−4.3 1.0 – – 1.0 –
3.0
4.5 1.1 – – 1.1 –
1.65 −1.95 – – 0.6 – 0.6
2.25
V
IL
Low level input voltage
−2.7 – – 0.6 – 0.6
3.0
−4.3 – – 0.7 – 0.7
4.5 – – 0.7 – 0.7
1.8
2.7 – 0.77 0.90 – 1.2
3.0 – 0.64 0.80 – 1.0
ON
Switch ON resistance
R
3.6 – 0.51 0.65 – 1.0
1.8
2.7 – 20 – – 500
3.0 – 15 – – 500
3.6 – 15 – – 500
ΔR
ON
ON resistance match between channels
(1)
1.8
R
FLAT
ON resistance flatness
(2)
2.7 – 0.50 – – 0.8
3.0 – 0.40 – – 0.6
3.6 – 0.25 – – 0.5
Sn OFF
OFF
state leakage
3.6
I
current
Sn ON state
I
ON
leakage
3.6
current
V
= V
S
CC
to VCC;
= 100 mA
I
S
at RON max
V
S
= 100 mA
I
S
V
= V
S
CC
to V
;
CC
= 100 mA
I
S
= -1.2 to
V
S
3.6 V = 3.6 to
V
D
-1.2 V
= -1.2 to
V
S
3.6 V = open
V
D
−5.5 V
−5.5 V
= 25 °C -40 to 85 °C
T
A
Min Typ Max Min Max
–3.804.60–7.0
– 50 – – 500
–3.5– –6.6
– -0.55 – -2 1 µA
– -0.55 – -2 1 µA
Unit
V
V
Ω
mΩ
Ω
Doc ID 14580 Rev 3 7/23
Page 8
Electrical characteristics STG5678
Table 6. DC specifications (continued)
Test conditions Value
Symbol Parameter
D ON state
I
leakage
D
current
IIH,I
SEL leakage
IL
current
V
(V)
3.6
3.6
CC
= open
V
S
= -1.2 V to
V
D
3.6 V
V
=3.6V or
SEL
GND
Min Typ Max Min Max
-0.1 0.1 -1 1 µA
= 25 °C -40 to 85 °C
T
A
–0.55– -2 1µA
Quiescent
I
CCLV
supply current low voltage
3.6
V
1SEL
1.80 V
, V
2SEL
=
– 7 – – 10 µA
driving
2.5 Quiescent supply
I
CC
1. Note 1: ΔRON = R
2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges.
3. When V
current
and V
1SEL
(3)
ON(max)
2SEL
3.6 – 8 – – 16
1.65
−4.5
- R
ON (min)
is both low, the ICC consumption will reduce to less than 0.1 µA (max)
V V
V
1SEL
CC
1SEL
= V
= V
2SEL
2SEL
=
=
GND
–5.6– –10
–0.05– –0.1
Unit
µA
8/23 Doc ID 14580 Rev 3
Page 9
STG5678 Electrical characteristics
Table 7. AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤ 5ns)
Test conditions Value
Symbol Parameter
Vcc
(V)
TA = 25°C -40 to 85°C
Min Typ Max Min Max
1.65 − 1.95 – 0.45 – – –
2.3
t
PLH
, t
PHL
Propagation delay
− 2.7 – 0.40 – – –
− 3.3 – 0.30 – – –
3.0
3.6 – 0.25 – – –
1.65 − 1.95 VS = 0.8 V – 220 265 – –
t
ON
Tur n O N time
− 2.7
V
3.0 − 3.3 – 110 135 – –
= 1.5 V
S
– 140 175 – –
2.3
3.6 – 105 130 – –
1.65 − 1.95 VS = 0.8 – 120 150 – –
t
OFF
Tur n O F F time
2.3
− 2.7
3.0 − 3.3 – 77 92 – –
V
S
= 1.5 V
–7792 – –
3.6 – 77 92 – –
− 1.95
1.65 = 35 pF
Break-
t
D
before-make time delay
2.3
− 2.7 – 66 – – –
3.0
− 3.3 – 40 – – –
C
L
R
L
V
S
= 50 Ω
= VCC/2
–120–––
3.6 – 30 – – –
1.65
− 1.95
–55–––
Unit
ns
ns
ns
ns
2.3
Charge
Q
injection
− 2.7 – 76 – – –
− 3.3 – 94 – – –
3.0
C
= 100 pF
L
V
GEN
= 0 V
pC
3.6 – 126 – – –
Doc ID 14580 Rev 3 9/23
Page 10
Electrical characteristics STG5678
Table 8. Analog switch characteristics (CL = 5 pF, RL = 50 Ω,)
Test conditions Value
Symbol Parameter
O
X
T
IRR
talk
HD
OFF isolation
Crosstalk
(2)
Total harmonic distortion
(1)
V
CC
(V)
2.7 − 3.6
2.7 − 3.6
− 3.6
2.7
VS = 1 V
RMS,
f = 100 kHz
= 1 V
V
S
RMS,
f = 1 MHz
= 1 V
V
S
RMS,
f = 5 MHz
VS = 1 V
RMS,
f = 100 kHz
= 1 V
V
S
RMS,
f = 1 MHz
= 1 V
V
S
RMS,
f = 5 MHz
R
= 32 Ω
L
= 0.5 V
V
IN
DC bias = 0
PP
Min Typ Max Min Max
–-86 – – –
–-70 – – –
–-54 – – –
–-96 – – –
–-87 – – –
–-74 – – –
–0.01 – – – %
f = 20 Hz to 20 kHz
R
= 50 Ω
BW -3dB bandwidth 2.7 − 3.6
C
C
Sn(OFF)
Control pin input
SEL
capacitance
OFF Sn port capacitance
3.3 f = 1 MHz – 12 – – – pF
3.3
L
Signal = 0 dBm
f = 1 MHz
–30 – – –MHz
–120 – – – pF
= 25 °C -40 to 85 °C
T
A
Unit
dB
dB
D port capacitance
C
when switch is
D
3.3 f = 1 MHz – 290 – – – pF
enabled
1. Off isolation = 20Log10 (VD/VS), VD = output. VS = input to off switch.
2. Crosstalk values are measured between two switches.
10/23 Doc ID 14580 Rev 3
Page 11
STG5678 Test circuit

5 Test circuit

Figure 4. ON resistance

I
DS
V
V
CC

Figure 5. OFF leakage

I
S(OFF)
A
V
SS
S1
VS
S2
IN
GND
GND
V
CC
D
CS14071
I
D(OFF)
D
A
V
D
S2
V
CC
IN
GND
CS14081
Doc ID 14580 Rev 3 11/23
Page 12
Test circuit STG5678

Figure 6. OFF isolation

V
CC
GND
V
S

Figure 7. Bandwidth

S1
S2
IN
GND
V
CC
S1
D
50 Ω
V
OUT
CS00381
V
OUT
S2
IN
V
CC
GND
12/23 Doc ID 14580 Rev 3
CS00371
Page 13
STG5678 Test circuit

Figure 8. Channel-to-channel crosstalk

Figure 9. Test circuit

2. CL= 5/35 pF or equivalent (includes jig and probe capacitance)
=50Ω or equivalent
3. R
L
4. R
T=ZOUT
of pulse generator (typically 50 Ω)
CS14091
Doc ID 14580 Rev 3 13/23
Page 14
Test circuit STG5678

Figure 10. Break-before-make time delay

Figure 11. Switching time and charge injection (V
C
= 100 pF)
L
GEN
=0V, R
=0 Ω, RL=1MΩ,
GEN

Figure 12. Turn on, turn off delay time

V
CC
S1
S2
IN
V
IN
GND
D
R
C
L
V
OUT
L
14/23 Doc ID 14580 Rev 3
Page 15
STG5678 Application hint

6 Application hint

6.1 Input signal dynamic range

The STG5678 negative analog switch allows input signals that fall below 0 V to pass through the switch without signal distortion. The input signal dynamic range VI consists of a positive-region and a negative-region.
The positive-region is limited by the level of V difference between V the operating range in the negative region.
For example, if V

Figure 13. Application diagram

CC
and 5.5 V. The effect of this is that, the higher the VCC, the smaller
CC
= 3.6 V, the input signal dynamic range is from -1.9 V to 3.6 V.
VCC
0V
VCC-5.5
. The negative-region is limited by the
VCC
Negative SW
VI
Negative region
Doc ID 14580 Rev 3 15/23
Page 16
Package mechanical data STG5678

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.

Figure 14. Package outline for Flip-chip 12

3
2
1
D C B A
Bottom view
16/23 Doc ID 14580 Rev 3
Page 17
STG5678 Package mechanical data

Table 9. Mechanical data for Flip-chip 12

Symbol
Min Typ Max
A 0.55 0.605 0.66
A1 0.17 0.205 0.24
A2 0.38 0.4 0.42
b 0.215 0.255 0.295
D 1.568 1.598 1.628
D1 – 1.2 –
E 1.168 1.198 1.228
E1 – 0.8 –
e 0.36 0.4 0.44
f 0.189 0.199 0.209
ccc – 0.05 –

Figure 15. Footprint recommendation

Millimeters
Doc ID 14580 Rev 3 17/23
Page 18
Package mechanical data STG5678

Figure 16. Package outline for Flip-chip 12 with back side coating

C
B
A
4
$

Table 10. Mechanical data for Flip-chip 12 with back side coating

Millimeters
Symbol
Min Typ Max
A 0.595 0.65 0.705
A1 0.165 0.20 0.235
A2 0.38 0.4 0.42
b 0.215 0.255 0.295
D 1.568 1.598 1.628
D1 – 1.2 –
E 1.168 1.198 1.228
E1 – 0.8 –
e 0.36 0.4 0.44
f 0.189 0.199 0.209
ccc – 0.05 –
N5_ME
18/23 Doc ID 14580 Rev 3
Page 19
STG5678 Package mechanical data

Figure 17. Footprint recommendation

A
B
C
1 2 3 4

Figure 18. Tape information

N5_FR
Doc ID 14580 Rev 3 19/23
Page 20
Package mechanical data STG5678

Figure 19. Tape orientation

User direction of feed
AM00745V1

Table 11. Reel measurement

Tape
width
(mm)
AN
W2 W3
W1
Max Min Max Min Max
8 180 54 8.4 +1.5/-0 14.4 7.9 10.9
20/23 Doc ID 14580 Rev 3
Page 21
STG5678 Package mechanical data

Figure 20. Reel information

Doc ID 14580 Rev 3 21/23
Page 22
Revision history STG5678

8 Revision history

Table 12. Document revision history

Date Revision Changes
01-Apr-2008 1 Initial release.
10-Sep-2008 2 Document status promoted from preliminary data to datasheet.
Modified: Figure 19 on page 20. Updated: Table 9 on page 17.
04-Jun-2010 3 Added: Flip-chip 12 with back side coating. Document reformatted.
22/23 Doc ID 14580 Rev 3
Page 23
STG5678
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Doc ID 14580 Rev 3 23/23
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