Page 1
Features
7AFER
■ High speed:
–t
= 130 ps (typ.) at VCC = 3.0 V
PD
–t
= 140 ps (typ.) at VCC = 2.3 V
PD
■ Ultra low power dissipation:
–I
= 0.2 μA (max.) at TA = 85 °C
CC
■ Low ON-resistance:
–R
–R
–R
■ Wide operating voltage range:
–V
■ 5 V tolerant and 1.8 V compatible threshold ON
digital control input at V
■ Latch-up performance exceeds 200 mA per
= 1.0 Ω (typ.) at VCC = 4.5 V
ON
= 1.2 Ω (typ.) at VCC = 3.0 V
ON
= 2.0 Ω (typ.) at VCC = 1.8 V
ON
(opr.) = 1.65 to 4.5 V single supply
CC
= 1.65 to 4.5 V
CC
JESD 78, Class II
■ ESD performance tested per JESD 22
– 2000 V human-body model
(A114-B, Class II)
– 200 V machine model (A115-A)
– 1000 V charged-device model (C101)
Description
The STG5123 is a high speed CMOS low voltage
single analog SPDT (single-pole double-throw)
switch or 2:1 multiplexer/demultiplexer switch
manufactured using silicon gate C
technology. Designed to operate from a 1.65 to
4.5 V supply, this device is ideal for portable
applications.
The device offers very low ON-resistance (1 Ω)
at V
= 4.5 V. Switch S1 is ON (connected to
CC
common ports Dn) when the SEL input is held
high, and OFF (state of high impedance exists
between the two ports) when SEL is held low.
2
MOS
STG5123
Low voltage 1 Ω single SPDT switch
with break-before-make feature
Datasheet − production data
DFN6L
Switch S2 is ON (connected to common port D)
when the SEL input is held low, and OFF (state
of high impedance exists between the two ports)
when SEL is held high.
Additional key features are fast switching speed,
break-before-make delay time and ultra low power
consumption. All inputs and outputs are equipped
with protection circuits to protect against static
discharge, giving them immunity from ESD and
transient excess voltage.
Table 1. Device summary
Order code Package Packaging
STG5123DTR
JSTG5123-CD1 Unsawn wafer
DFN6L
(1.2 x 1 mm)
Tape and reel
April 2012 Doc ID 14102 Rev 5 1/22
This is information on a product in full production.
www.st.com
1
Page 2
Contents STG5123
Contents
1 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Die description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22 Doc ID 14102 Rev 5
Page 3
STG5123 List of tables
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. AC electrical characteristics (C
Table 8. Analog switch characteristics (C
Table 9. DFN6L (1.2 x 1 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Pad information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
= 35 pF, RL = 50 Ω, tr = tf ≤ 5 ns). . . . . . . . . . . . . . . . . . . . 8
L
= 5 pF, RL = 50 Ω, TA = 25 °C) . . . . . . . . . . . . . . . . . . . . 9
L
Doc ID 14102 Rev 5 3/22
Page 4
List of figures STG5123
List of figures
Figure 1. Pin connections (top through view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. ON-resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. OFF leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Channel-to-channel crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. OFF isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Break-before-make time delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Switching time and charge injection
(V
= 0 V, R
Figure 11. Turn-on, turn-off delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. DFN6L (1.2 x 1 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. DFN6L (1.2 x 1 mm) footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. DFN6L carrier tape information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. DFN6L reel information drawing (back view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. DFN6L reel information drawing (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. JSTG5123-CD1 die plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
GEN
= 0 Ω, RL = 1 MΩ, CL = 100 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
GEN
4/22 Doc ID 14102 Rev 5
Page 5
STG5123 Pin connections and functions
1 Pin connections and functions
Figure 1. Pin connections (top through view)
Table 2. Pin descriptions
Pin number Symbol Name and function
4 S1 Independent channel
6 S2 Independent channel
1 D Common channels
3 SEL Control
2V
CC
5 GND Ground (0 V)
Positive supply voltage
Figure 2. Input equivalent circuit
Table 3. Truth table
Sel Switch S1 Switch S2
HONOFF
LOFF
1. High impedance.
Doc ID 14102 Rev 5 5/22
(1)
S2
S1
(1)
ON
Page 6
Electrical ratings STG5123
2 Electrical ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 5: Recommended
operating conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics™ SURE program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
I
CC
V
V
V
V
I
IKC
I
I
OK
I
I
OP
or I
P
T
STG
T
CC
IC
O
IK
O
D
L
Supply voltage –0.5 to 5.5 V
DC input voltage –0.5 to V
I
CC
DC control input voltage –0.5 to 5.5 V
DC output voltage –0.5 to V
DC input diode current on control pin (V
DC input diode current (V
< 0 V) ±50 mA
IN
< 0 V) –50 mA
SEL
CC
DC output diode current ±20 mA
DC output current ±200 mA
DC output current peak
(pulse at 1 ms, 10% duty cycle)
DC VCC or ground current ±100 mA
GND
Power dissipation at TA = 70 °C
(1)
±400 mA
1120 mW
Storage temperature –65 to 150 °C
Lead temperature (10 s) 300 °C
+0.5 V
+0.5 V
1. Derate above 70 °C by 18.5 mW/°C.
Table 5. Recommended operating conditions
Symbol Parameter Value Unit
V
CC
V
V
IC
V
O
T
op
dt/dv
I
Supply voltage 1.65 to 4.5 V
Input voltage 0 to V
Control input voltage 0 to 4.5 V
Output voltage 0 to V
Operating temperature –40 to 85 °C
V
= 1.65 to 2.7 V 0 to 20
Input rise and fall time
control input
CC
V
= 3.0 to 4.5 V 0 to 10
CC
6/22 Doc ID 14102 Rev 5
CC
CC
V
V
ns/V
Page 7
STG5123 Electrical characteristics
3 Electrical characteristics
3.1 DC electrical characteristics
Table 6. DC specifications
Value
Symbol Parameter V
1.65 – 1.95 0.65 V
2.3 – 2.5 1.2 1.2
V
High level input
IH
voltage
2.7 – 3.0 1.3 1.3
3.3 – 3.6 1.4 1.4
1.65 – 1.95 0.40 0.40
2.3 – 2.5 0.60 0.60
IL
Low level input
voltage
2.7 – 3.0 0.60 0.60
V
3.3 – 3.6 0.60 0.60
ON
Switch ONresistance
R
ON-resistance
ΔR
match between
ON
channels
(1)
(V) Test condition
CC
Min. Typ. Max. Min. Max.
CC
0.65 V
CC
4.5 1.6 1.6
4.5 0.80 0.80
1.8
2.7 1.3 1.6 1.8
3.0 1.2 1.5 1.7
V
= 0 V to V
S
IS = 100 mA
CC
2.0 3.0 3.5
4.5 1.0 1.2 1.4
1.8
2.7 0.05
3.0 0.05
V
at RON max
S
= 100 mA
I
S
0.06
4.5 0.05
1.8
1.0 1.5 1.5
UnitTA = 25 °C -40 to 85 °C
V
V
Ω
Ω
R
FLAT
I
OFF
I
I
CC
IN
ON-resistance
flatness
(2)
OFF state
leakage current
(Sn), (D)
Input leakage
current
Quiescent
supply current
2.7 0.45 0.60 0.70
3.0 0.43 0.50 0.60
= 0 V to V
V
S
IS = 100 mA
CC
4.5 0.39 0.50 0.60
4.3 V
0 – 4.5 V
1.65 – 4.5
= 0.3 or 4 V ±20 ±100 nA
S
= 0 to 4.5 V ±0.1 ±1.0 μA
SEL
V
= VCC or
SEL
GND
±0.1 ±1.0 μA
Doc ID 14102 Rev 5 7/22
Ω
Page 8
Electrical characteristics STG5123
Table 6. DC specifications (continued)
Value
Symbol Parameter V
(V) Test condition
CC
Min. Typ. Max. Min. Max.
Quiescent
I
CCLV
supply current
low voltage
driving
1. ΔRON = R
2. Flatness is defined as the difference between the maximum and minimum value of ON-resistance as measured over the
specified analog signal ranges.
ON(Max)
- R
ON(Min)
4.3 V
4.3 V
.
= 1.65 V ±17 ±35 ±70
SEL
= 1.80 V ±15 ±30 ±60
SEL
= 2.60 V ±5 ±10 ±20
SEL
3.2 AC electrical characteristics
Table 7. AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤
Symbol Parameter
, t
t
PLH
Propagation delay
PHL
V
CC
(V)
Test
conditions
= 25 °C – 40 to 85 °C
A
Min. Typ. Max. Min. Max.
1.65 – 1.95 0.15
2.3 – 2.7 0.14
3.0 – 3.3 0.13
5 ns)
Value
UnitTA = 25 °C -40 to 85 °C
μA4.3 V
UnitT
ns
t
t
OFF
ON
t
Tu r n- O N ti m e
Turn-OFF time
Break-before-
D
make time delay
Q Charge injection
3.6 – 5.0 0.13
1.65 – 1.95 V
2.3 – 2.7
3.0 – 3.3 24 31 40
= 0.8 V 36
S
V
= 1.5 V
S
31 40 45
3.6 – 5.0 21 28 32
1.65 – 1.95 V
2.3 – 2.7
3.0 – 3.3 12 23 33
= 0.8 V 29
S
= 1.5 V
V
S
17 27 37
3.6 – 5.0 11 21 31
1.65 – 1.95
C
= 35 pF
2.3 – 2.7 10
3.0 – 3.3 8
L
R
L
V
S
= 50 Ω
= 1.5 V
15
3.6 – 5.0 6
1.65
= 100 pF
C
2.3 22
326
V
R
L
GEN
GEN
= 0 V
= 0 Ω
16
5.0 33
ns
ns
ns
pC
8/22 Doc ID 14102 Rev 5
Page 9
STG5123 Electrical characteristics
3.3 Analog switch characteristics
Table 8. Analog switch characteristics (CL = 5 pF, RL = 50 Ω, TA = 25 °C)
Value
Symbol Parameter V
OIRR OFF isolation
(1)
CC
1.65 – 5.0
Xtalk Crosstalk 1.6 – 5.0
THD
Total harmonic
distortion
2.3 – 5.0
(V)
Test
conditions
= 1 V
V
S
RMS
f = 100 kHz
= 1 V
V
S
RMS
f = 100 kHz
R
= 600 Ω
L
= 2 V
V
S
PP
f = 20 Hz to
20 kHz
= 25 °C -40 to 85 °C
A
Min. Typ. Max. Min. Max.
– 75 dB
– 80 dB
0.03 %
UnitT
BW -3 dB bandwidth 1.65 – 5.0 R
C
Control pin input
IN
capacitance
= 50 Ω 150 MHz
L
Sn port
ON
capacitance
when switch is
C
3.3 f = 1 MHz 52
enabled
Sn port
OFF
capacitance
when switch is
3.3 f = 1 MHz 25
C
disabled
D port
C
capacitance
D
when switch is
3.3 f = 1 MHz 50
enabled
1. OFF isolation = 20 log10 (VD/VS), VD = output. VS = input to OFF switch.
6
pF
Doc ID 14102 Rev 5 9/22
Page 10
Test circuits STG5123
4 Test circuits
Figure 3. ON-resistance
)
$3
6
6
##
63
'.$
Figure 4. Bandwidth
3
3
3
).
'.$
6
##
$
#36
$
6
/54
3
6
3
10/22 Doc ID 14102 Rev 5
6
).
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'.$
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Page 11
STG5123 Test circuits
Figure 5. OFF leakage
6
##
)
3/&&
!
6
33
3
).
6
##
Figure 6. Channel-to-channel crosstalk
6
/54
3
'.$
6
##
)
$/&&
$
!
6
$
#36
$
3
6
3
6
##
).
'.$
#36
Doc ID 14102 Rev 5 11/22
Page 12
Test circuits STG5123
Figure 7. OFF isolation
6
##
'.$
6
3
Figure 8. Test circuit
05,3%
'%.%2!4/2
3
3
).
'.$
$54
6
/54
#36
6
##
2
4
1. CL = 5/35 pF or equivalent: (includes jig capacitance).
= 50 Ω or equivalent.
2. R
L
= Z
3. R
T
of pulse generator (typically 50 Ω).
OUT
12/22 Doc ID 14102 Rev 5
#
2
,
,
3#6
Page 13
STG5123 Test circuits
#3V
6
##
'.$
6
).
6
/54
T
/&&
T
/.
Figure 9. Break-before-make time delay
6
##
3
6
3
3
).
6
).
'.$
$
2
,
6
/54
#
,
#3V
Figure 10. Switching time and charge injection
(V
6
'%.
= 0 V, R
GEN
2
'%.
3
3
).
6
).
= 0 Ω, RL = 1 MΩ, CL = 100 pF)
GEN
6
##
$
2
,
'.$
6
/54
#
,
#36
Figure 11. Turn-on, turn-off delay time
6
##
6
6
).
/54
3
3
).
6
).
'.$
$
2
,
6
/54
#
,
#36
Doc ID 14102 Rev 5 13/22
T
/&&
T
/.
6
##
'.$
#36
Page 14
Package information STG5123
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 12. DFN6L (1.2 x 1 mm) package outline
1. Drawing is not to scale.
14/22 Doc ID 14102 Rev 5
7899067
Page 15
STG5123 Package information
Table 9. DFN6L (1.2 x 1 mm) mechanical data
Dimensions (millimeters)
Symbol
Typ. Min. Max.
A 0.50 0.45 0.55
A1 0.02 0 0.05
A3 0.127
b 0.20 0.15 0.25
D 1.20 1.15 1.25
E 1 0.95 1.05
e 0.40
L 0.35 0.30 0.40
L1 0.45 0.40 0.50
Figure 13. DFN6L (1.2 x 1 mm) footprint recommendation
Doc ID 14102 Rev 5 15/22
Page 16
Package information STG5123
Figure 14. DFN6L carrier tape information
1. Measured from centreline of sprocket hole to centreline of pocket.
2. Cumulative tolerance of 10 sprocket holes is ±
3. Measured from centreline of sprocket hole to centreline of pocket.
4. Other material available.
5. Drawing is not to scale.
6. All dimensions are in millimeters unless otherwise stated.
0.20.
16/22 Doc ID 14102 Rev 5
Page 17
STG5123 Package information
Figure 15. DFN6L reel information drawing (back view)
!-
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Doc ID 14102 Rev 5 17/22
Page 18
Package information STG5123
Figure 16. DFN6L reel information drawing (front view)
1. Drawing not to scale.
2. Dimensions are in millimeters.
18/22 Doc ID 14102 Rev 5
Page 19
STG5123 Die description
6 Die description
Product JSTG5123-CD1
● Wafer size: 203 mm (8 inches)
● Wafer thickness: 725 μm + 25 μm
● Die identification: V891A.
Die layout
● Design die size (X x Y): 900 x 350 μm
● Scribe line: 100 x 62 μm
● Stepping die size: 1000 x 412 μm
● Pad opening: 76 x 76 μm
● DI: die identification (at the position shown in Figure 17)
● Pads: pad contact (at the position shown in Figure 17 and Ta b le 1 0 ).
Figure 17. JSTG5123-CD1 die plot
3
$
6!
$IEIDENTIFICATION
Refer to Tab le 1 0 for the pad locations.
8 9
'.$
6
##
3
3%,
!-
Doc ID 14102 Rev 5 19/22
Page 20
Die description STG5123
Table 10. Pad information
Pad function X (μm) Y(μm)
S2 -292.25 52
GND 96.75 86
S1 292.25 52
SEL 361 -52
V
CC
96.75 -18
D -292.25 -52
Pad locations are measured relative to the die center (where X and Y are the horizontal and
vertical axis, respectively, measured in μm). Refer to Figure 17.
20/22 Doc ID 14102 Rev 5
Page 21
STG5123 Revision history
7 Revision history
Table 11. Document revision history
Date Revision Changes
30-Oct-2007 1 Initial release.
Table 6: DC specifications on page 7: Modified values for “Input
21-Apr-2010 2
leakage current” and “Quiescent supply current”.
Updated ECOPACK
information.
Minor text changes throughout the document.
®
statement in Section 5: Package
08-Feb-2011 3
21-Dec-2011 4
02-Apr-2012 5
Corrected typo in Tab le 2, Section 2, Ta b l e 6 to Tab le 9 ,
Figure 12, updated Figure 14.
Added wafer, Section 6: Die description, updated Ta bl e 1 ,
Section 2: Electrical ratings and Disclaimer, minor text
corrections throughout document.
Added product maturity information, updated Ta ble 1 and
Section 6 (replaced RPN JTS5123-CD1 by JSTG5123-CD1),
minor text corrections throughout document.
Doc ID 14102 Rev 5 21/22
Page 22
STG5123
y
Please Read Carefully:
Informatio n in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at an
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or imp lied, by estoppel or otherwise, to any intellectual property rights is granted under this do cument. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
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OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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22/22 Doc ID 14102 Rev 5
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