break-before-make feature and 15 kV contact ESD protection
Features
■ Wide operating voltage range:
V
(opr) = 1.65 to 4.8 V
CC
■ Low power dissipation:
I
= 0.2 µA (max.) at TA = 85 °C
CC
■ Low "ON" resistance:
–R
–R
–R
■ Separate supply voltage for switch and control
pins
■ Latch-up performance exceeds 100mA per
JESD 78, Class II
■ ESD performance tested on common pin
(D pin):
– 15 kV IEC-61000-4-2 ESD, contact
– 8 kV HBM JESD22 A114-B Class II
■ ESD performance tested on S1 and S2 pin:
– 8 kV IEC-61000-4-2 ESD, contact
■ ESD performance test on all other pins:
– 4 kV HBM (JESD22 A114-B Class II)
– 400 V machine model (JESD22 A115-A)
– 1500 V charged-device model
Applications
■ Mobile phones
Table 1.Device summary
= 0.75 Ω (TA = 25 ºC)
ON
at V
at V
at V
= 2.25 V
CC
= 0.50 Ω (TA = 25 ºC)
ON
= 3.0 V
CC
=0.40Ω (TA =25ºC)
ON
=4.3V
CC
discharge
discharge
(JESD22 C101)
STG4160
Flip-chip 8
Description
The STG4160 is a high-speed CMOS low voltage
single analog SPDT (single pole dual throw)
switch or 2:1 multiplexer/demultiplexer switch
fabricated in silicon gate C
designed to operate from 1.65 to 4.8 V, making
this device ideal for portable applications. It offers
low ON resistance (0.40 Ω typ.) at V
The SEL inputs are provided to control the
switches.
The switch S1 is ON (connected to common port
D) when the SEL input is held high and OFF (high
impedance state exists between the two ports)
when SEL is held low. The switch S2 is ON
(connected to common Port D) when the SEL
input is held low and OFF (high impedance state
exist between the two ports) when SEL is held
high.
Additional key features are fast switching speed,
break-before-make delay time and ultra power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.Absolute maximum ratings
SymbolParameterValueUnit
V
CC
V
V
V
V
I
IKC
I
IK
I
OK
I
O
I
OP
I
or I
CC
P
T
stg
T
1. Derate above 70 ºC by 18.5 mW/C
Table 5.Recommended operating conditions
Supply voltage-0.5 to 5.5V
Logic supply voltage-0.5 to 5.5V
L
DC input voltage-0.5 to VCC +0.5V
I
DC control input voltage-0.5 to VL +5.5V
IC
DC output voltage-0.5 to VCC +0.5V
O
DC input diode current on control pin (V
DC input diode current (V
<0V)±50mA
SEL
<0V)-50mA
SEL
DC output diode current± 20mA
DC output current± 300mA
DC output current peak (pulse at 1ms, 10% duty cycle)± 500mA
DC VCC or ground current± 100mA
GND
Power dissipation at TA= 70ºC
D
(1)
500mW
Storage temperature-65 to 150°C
Lead temperature (10 sec)260°C
L
SymbolParameterValueUnit
V
V
V
V
V
T
dt/dv
1. VL pin should not be left floating.
Supply voltage1.65 to 4.8V
CC
Logic supply voltage
L
Input voltage0 to V
I
Control input voltage0 to V
IC
Output voltage0 to V
O
Operating temperature-40 to 85°C
op
Input rise and fall time control
input
(1)
1.65 to V
= 1.65 to 2.7 V0 to 20
V
L
= 3.0 to 4.8 V0 to 10
V
L
CC
CC
L
CC
V
V
V
V
ns/V
5/19
Page 6
Electrical characteristicsSTG4160
4 Electrical characteristics
Table 6.DC specifications
SymbolParameter
V
IH
V
IL
High level
input voltage
Low level
input voltage
V
CC
(V)
1.65 – 4.3
1.65 – 4.3
1.8
2.250.751.01.3
ON
ON resistance
R
30.500.650.8
3.70.450.550.7
4.30.400.50.65
1.8
2.2520
310
3.710
ΔR
ON resistance
match
ON
between
channels
(1)
4.310
Val ue
V
(V)
L
Test condition
= 25 °C-40 to 85 °C
A
MinTypMaxMinMax
1.65 – 1.951.251.25
2.3 – 2.71.751.75
3.0 – 3.62.342.34
4.32.802.80
1.65 – 1.950.60.6
2.3 – 2.70.80.8
3.0 – 3.61.051.05
4.31.51.5
1.52.53.7
=0V to
V
S
1.65 – 4.3
V
CC
IS=100mA
40
=0V to
V
S
1.65 – 4.3
V
CC
IS=100mA
UnitT
V
V
Ω
mΩ
1.8
R
FLAT
ON resistance
flatness
(2)
2.25300430550
3150190270
1.65 – 4.3
3.7140180230
VS=0V to
V
CC
IS=100mA
4.3140180220
I
OFF
I
ON
I
D
Sn OFF state
leakage
current
Sn ON state
leakage
current
D ON state
leakage
current
4.34.3
4.34.3
4.34.3
VS= 0.3 to 4.0
V
D
VS= 0.3 to 4.0
V
D
VS= open
V
D
6/19
= 0.3 to 4.0
= open
= 0 to 4.0
1.01.72.0
mΩ
-3030-300300nA
-3030-300300nA
-3030-300300nA
Page 7
STG4160Electrical characteristics
Table 6.DC specifications (continued)
Val ue
SymbolParameter
V
CC
(V)
V
(V)
L
Test condition
= 25 °C-40 to 85 °C
A
MinTypMaxMinMax
UnitT
CC
Quiescent
supply current
SEL leakage
current
- R
ON(Max)
ON(Min)
1.65 – 4.31.65 – 4.3
1.65 – 4.31.65 – 4.3
I
I
SEL
1. ΔRON = R
2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog
signal ranges.
1. OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch
-3dB Bandwidth
(switch ON)
1.65 – 4.34.3R
= 50 Ω50MHz
L
TA = 25°C-40 to 85°C
MinTypMaxMinMax
75
77
67
50
80
67
50
0.01%
Unit
pC
dB
dB
8/19
Page 9
STG4160Electrical characteristics
Table 8.Capacitive characteristics
Test conditionValue
SymbolParameter
V
CC
(V)
Control pin
C
SEL
input
1.8 –4.3 1.8–4.3 VL=V
capacitance
SN
Sn port
capacitance
1.8–4.3 1.8–4.3 V
C
D port
C
capacitance
D
when the switch
1.8– 4.3 1.8–4.3 V
is enabled
V
(V)
T
= 25 °C-40 to 85 °C
L
A
Unit
MinTypMaxMinMax
CC
L=VCC
L=VCC
30pf
94pf
227pf
9/19
Page 10
Test circuitsSTG4160
5 Test circuits
Figure 4.ON resistance
I
DS
V
V
CC
VS
GND
Figure 5.Bandwidth
S1
S2
IN
GND
V
CC
S1
D
CS14071
D
V
OUT
S2
IN
V
CC
10/19
GND
CS00371
Page 11
STG4160Test circuits
Figure 6.OFF leakage
V
CC
I
S(OFF)
A
V
SS
S2
V
CC
Figure 7.Channel-to-channel crosstalk
IN
GND
I
D(OFF)
D
A
V
D
CS14081
CS14091
11/19
Page 12
Test circuitsSTG4160
Figure 8.OFF isolation
V
CC
GND
V
S
Figure 9.Test circuit
S1
S2
IN
GND
50 Ω
V
OUT
CS00381
1. CL = 5/35 pF or equivalent: (includes jig capacitance)
= 50 Ω or equivalent
2. R
L
= Z
3. R
T
of pulse generator (typically 50 Ω )
OUT
12/19
Page 13
STG4160Test circuits
Figure 10. Break-before-make time delay
Figure 11. Switching time and charge injection
(V
GEN
=0V, R
=0Ω, RL=1MΩ, CL= 100 pF)
GEN
Figure 12. Turn ON, turn OFF delay time
13/19
Page 14
Package mechanical dataSTG4160
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 13. Flip-chip 8 package outline
1. Drawing not to scale.
14/19
Page 15
STG4160Package mechanical data
Table 9.Flip-chip 8 mechanical data
Millimeters
Symbol
MinTypMax
A0.535 0.58 0.625
A10.18 0.205 0.23
A20.355 0.375 0.395
b0.2150.2550.295
D1.85 1.9 1.95
D11.5
e0.45 0.5 0.55
E0.850.90.95
E10.45 0.5 0.55
SE0.25
f0.190.20.21
ccc0.08
Figure 14. Flip-chip 8 footprint
GRID PLACEMENT AREA
A
B
1.5
0.5
12
3
0.5
4
0.22
15/19
Page 16
Package mechanical dataSTG4160
Figure 15. Flip-chip 8 tape and reel
Figure 16. Tape orientation
5SERDIRECTIONOFFEED
!-6
!-6
16/19
Page 17
STG4160Package mechanical data
Figure 17. Reel information
17/19
Page 18
Revision historySTG4160
7 Revision history
Table 10.Document revision history
DateRevisionChanges
11-Sep-20081Initial release.
19-Feb-20092Updated: ION values in Table 6: DC specifications.
18/19
Page 19
STG4160
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