Page 1
Low voltage 0.3 Ω max single SPDT switch with
break-before-make feature and 10 kV contact ESD protection
Features
■ Wide operating voltage range:
V
(opr) = 1.65 V to 4.8 V
CC
■ Low power dissipation:
I
= 0.2 µA (max.) at TA = 85 °C
CC
■ Low “ON” resistance V
–R
–R
–R
■ Separate supply voltage for switch and control
= 0.40 Ω (max. TA = 25 °C) at
ON
V
= 2.25 V
CC
= 0.35 Ω (max. TA = 25 °C) at
ON
V
= 3.0 V
CC
= 0.30 Ω (max. TA = 25 °C) at
ON
V
= 4.3 V
CC
pin
■ Latch-up performance exceeds 100 mA per
JESD 78, class II
■ ESD performance tested on common channel
(D pin)
– 10 kV IEC-61000-4-2 ESD, contact
discharge
– 15 kV IEC-61000-4-2 ESD, air discharge
■ ESD performance test on all other pins
– 10 kV IEC-61000-4-2 ESD, contact
discharge
– 500 V machine model (JESD22 A115-A)
– 1500 V charged-device model
(JESD22 C101)
= 0 V:
IN
STG4159
Flip-chip 7
Description
The STG4159 is a high-speed CMOS low voltage
single analog SPDT (single pole dual throw)
switch or 2:1 multiplexer/demultiplexer switch
fabricated in silicon gate C
designed to operate from 1.65 V to 4.8 V, making
this device ideal for portable applications. It offers
low ON-resistance (0.30 Ω) at V
SEL inputs are provided to control the switches.
The switch S1 is ON (connected to common port
D) when the SEL input is held high and OFF (high
impedance state exists between the two ports)
when SEL is held low; the switch S2 is ON (it is
connected to common port D) when the SEL input
is held low and OFF (high impedance state exist
between the two ports) when SEL is held high.
Additional key features are fast switching speed,
break-before-make delay time and ultra low power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.
2
MOS technology. It is
= 4.3 V. The
CC
Table 1. Device summary
Order code Package Packaging
STG4159BJR Flip-chip 7 Tape and reel
October 2009 Doc ID 12493 Rev 5 1/18
www.st.com
18
Page 2
Contents STG4159
Contents
1 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18 Doc ID 12493 Rev 5
Page 3
STG4159 Logic diagram
1 Logic diagram
Figure 1. Functional diagram
D
Figure 2. Input equivalent circuit
$N
S1
S2
SEL
N3
N3
3%,
Table 2. Truth table
SEL Switch S1 Switch S2
HONOFF
LOFF
1. High impedance.
!-6
(1)
(1)
Doc ID 12493 Rev 5 3/18
ON
Page 4
Logic diagram STG4159
Figure 3. STG4159 pin connections
"UMPVIEW 4OPVIEW
6,
3
3
Table 3. Pin assignment
Pin number Symbol Name and function
1 S1 Independent channels
3 S2 Independent channels
4V
5V
6 SEL Control
6##
3%,
$
'.$
CC
3
3
6,
L
Logic supply voltage
$
3%,
6
Positive supply voltage
7 D Common channel
8 GND Ground (0 V)
4/18 Doc ID 12493 Rev 5
Page 5
STG4159 Maximum rating
2 Maximum rating
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
V
V
V
IC
V
O
I
IKC
I
IK
I
OK
I
O
I
OP
or I
I
CC
P
T
stg
T
1. Derate above 70 °C by 18.5 mW/C
Supply voltage -0.5 to 5.5 V
Logic supply voltage -0.5 to 5.5 V
L
DC input voltage -0.5 to VCC + 0.5 V
I
DC control input voltage -0.5 to VL + 0.5 V
DC output voltage -0.5 to VCC + 0.5 V
DC input diode current on control pin (V
DC input diode current (V
< 0V) ±50 mA
SEL
SEL
DC output diode current ±20 mA
DC output current ±300 mA
DC output current peak (pulse at 1 ms, 10% duty cycle) ±500 mA
DC VCC or ground current ±100 mA
GND
Power dissipation at TA = 70°C
D
(1)
Storage temperature -65 to 150 °C
Lead temperature (10 sec) 260 °C
L
Table 5. Recommended operating conditions
< 0V) -50 mA
500 mW
Symbol Parameter Value Unit
V
CC
V
V
V
IC
V
O
T
op
dt/dv Input rise and fall time control input
1. VL pin should not be left floating.
Supply voltage 1.65 to 4.8 V
Logic supply voltage
L
Input voltage 0 to V
I
(1)
1.65 to V
Control input voltage 0 to V
Output voltage 0 to V
Operating temperature -40 to 85 °C
V
= 1.65 V to 2.7 V 0 to 20
L
= 3.0 V to 4.8 V 0 to 10
V
L
CC
CC
L
CC
Doc ID 12493 Rev 5 5/18
V
V
V
V
ns/V
Page 6
Electrical characteristics STG4159
3 Electrical characteristics
Table 6. DC specifications
Test conditions Value
Symbol Parameter
V
V
R
ΔR
High level input
IH
voltage
Low level input
IL
voltage
ON resistance
ON
ON resistance
match between
ON
channels
(1)
VCC
(V)
1.65 - 4.3
1.65 - 4.3
1.8
2.25
3
3.7
4.3
1.8
2.25
3 − 3 −− −
3.7 − 3 −−−
4.3 − 3 −−−
1.8
VL
(V)
1.65 - 1.95 1.25
2.3 - 2.7 1.75
3.0 - 3.6 2.35 −−2.35 −
4.3 2.8 −−2.8 −
1.65 - 1.95
2.3 - 2.7
3.0 - 3.6
4.3
V
= 0 V to V
1.65 - 4.3
1.65 - 4.3
S
IS=100mA
V
= 0 V to V
S
IS=100 mA
CC
CC
TA = 25°C -40 to 85°C
Min. Typ. Max. Min. Max.
−−1.25 −
−−1.75 −
−−0.6 − 0.6
−−0.8 − 0.8
−−1.05 − 1.05
−−1.5 − 1.5
− 0.49 0.65 − 0.85
− 0.30 0.40 − 0.50
− 0.25 0.35 − 0.45
− 0.22 0.32 − 0.42
− 0.21 0.30 − 0.40
− 5 −−−
− 3 −−−
− 300 400 − 450
Unit
V
V
Ω
mΩ
2.5
V
= 0 V to V
S
IS=100 mA
= 0.3 to 4.0
V
S
= 0.3 to 4.0
V
D
= 0.3 to 4.0
V
S
=Open
V
D
= Open
V
S
= 0.3 to 4.0
V
D
ON
I
D
ON resistance
flatness
Sn OFF state
leakage current
Sn ON state
leakage current
D ON state
leakage current
(2)
3
3.7
4.3
1.65 - 4.3 1.65 - 4.3
1.65 - 4.3 1.65 - 4.3
1.65 - 4.3 1.65 - 4.3
R
FLAT
I
OFF
I
6/18 Doc ID 12493 Rev 5
1.65 - 4.3
− 130 170 − 230
CC
− 90 120 − 170
− 90 120 − 170
− 90 120 − 170
-30
-20
-20
− 30 -300 300 nA
− 20 -100 100 nA
− 20 -100 100 nA
mΩ
Page 7
STG4159 Electrical characteristics
Table 6. DC specifications (continued)
Test conditions Value
Symbol Parameter
I
I
SEL
1. ΔRON = R
2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Table 7. AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤ 5 ns)
Quiescent supply
CC
current
SEL leakage
current
ON(Max)
- R
ON(Min)
V
CC
(V)
V
(V)
L
1.65 - 4.3 1.65 - 4.3
1.65 - 4.3 1.65 - 4.3
V
SEL=VCC
GND
V
=4.3V or
SEL
GND
or
= 25°C -40 to 85°C
T
A
Min. Typ. Max. Min. Max.
-0.05
-0.1
− 0.05 -0.2 0.2 µA
− 0.1 -1 1 µA
Test conditions Value
Symbol Parameter
, t
PHL
Propagation
delay
t
PLH
V
CC
(V)
V
(V)
L
1.65 - 1.95
2.3 - 2.7
1.65-4.3
3.0 - 3.3 − 0.16 −− −
TA = 25°C -40 to 85°C
Min. Typ. Max. Min. Max.
− 0.13 −− −
− 0.15 −− −
3.6 - 4.3 − 0.16 −− −
− 95 123 − 160
− 48 62 − 80
− 33 43 − 56
− 29 38 − 49
t
ON
TURN-ON time
1.65 - 1.95
2.3 - 2.7
3-3.6
4.3
1.65-4.3
VS = V
CC
RL = 50 Ω
= 30 pF
C
L
Unit
Unit
ns
ns
t
D
TURN-OFF time
Break-beforemake time delay
t
OFF
Q Charge injection
1.65 - 1.95
V
= V
S
2.3 - 2.7
1.65-4.3
3-3.6
CC
RL = 50 Ω
C
= 30 pF
L
4.3
1.65 - 1.95
C
= 35 pF
2.3 - 2.7 10 22
1.65-4.3
3-3.6 5 15 −−−
L
R
L
V
S
= 50 Ω
= VCC/2
− 12 15 − 20
− 12 16 − 21
− 13 17 − 22
− 13 17 − 22
10 42 −− −
−−−
4.3 5 12 −−−
1.65 - 1.95
2.3 - 2.7 − 98 −− −
1.65-4.3
3.0 - 3.3 − 114 −− −
CL = 1nF
= 0 V
V
GEN
− 83 −− −
3.6 - 4.3 − 140 −− −
Doc ID 12493 Rev 5 7/18
ns
ns
pC
Page 8
Electrical characteristics STG4159
Table 8. Analog switch characteristics (CL = 5 pF, RL = 50 Ω, TA = 25 °C)
Test conditions Value
Symbol Parameter
OIRR Off Isolation
Xtalk Crosstalk 1.65 - 4.3 4.3
THD
BW
C
C
C
Total harmonic
distortion
-3dB bandwidth
(switch ON)
Control pin input
SEL
capacitance
Sn port
Sn
capacitance
D port
capacitance
D
when switch is
enabled
(1)
V
CC
(V)
1.65 - 4.3 4.3
2.3 - 4.3 4.3
1.65 - 4.3 4.3 R
1.8 - 4.3 1.8 - 4.3 V
1.8 - 4.3 1.8 - 4.3 V
1.8 - 4.3 1.8 - 4.3 V
V
(V)
L
V
= 1V
S
RMS
f = 100 kHz
V
= 1V
S
RMS
f = 100 kHz
= 600 Ω
R
L
= 50 pF
C
L
= VCC V
V
S
f = 600 Hz to
20 kHz
= 50 Ω
L
= V
L
= V
L
= V
L
PP
CC
CC
CC
= 25°C -40 to 85°C
T
A
Min. Typ. Max. Min. Max.
− -69 −−−dB
-69
−
0.01
−
28
−
30
−
94
−
227
−
−−−
−−−
−−−
−−−
−−−
−−−
Unit
dB
%
MHz
pF
1. OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch.
8/18 Doc ID 12493 Rev 5
Page 9
STG4159 Test circuits
V
4 Test circuits
Figure 4. ON-resistance Figure 5. Bandwidth
Figure 6. OFF Leakage Figure 7. Channel to channel crosstalk
AM04072V1
AM04073V1
AM04074V1
Figure 8. OFF Isolation
Doc ID 12493 Rev 5 9/18
Page 10
Test circuits STG4159
Figure 9. Test circuit
Note: 1 CL = 5/35 pF or equivalent: (includes jig capacitance)
2R
3R
Figure 10. Break-before-make time delay
= 50 Ω or equivalent
L
= Z
T
of pulse generator (typically 50 Ω)
OUT
V
= 0 V, R
GEN
Figure 11. Switching time and charge injection
= 0 Ω, RL = 1 MΩ, CL = 100 pF
GEN
10/18 Doc ID 12493 Rev 5
Page 11
STG4159 Test circuits
Figure 12. Turn ON, turn OFF delay time
Doc ID 12493 Rev 5 11/18
Page 12
Package mechanical data STG4159
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
Figure 13. Flip-chip 7 mechanical data
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Millimeters
Symbol
Min Typ Max
A 0.585 0.65 0.715
A1 0.21 0.25 0.29
A2
b 0.265 0.315 0.365
D 1.018 1.068 1.118
D1
E 2.018 2.068 2.118
E1
e 0.45 0.5 0.55
f
−
−
−
−
0.4
0.5
1.5
0.284
−
−
−
−
ccc
−
0.08
−
Note: The terminal pin 1 on the bumps side is identified by a distinguishing feature (for instance by
a circular “clear area” - typically 0.1 mm diameter -) The terminal pin 1 on the backside of
the product is identified by a distinguishing feature (for instance by a circular “dot” - typically
0.5 mm diameter -)
12/18 Doc ID 12493 Rev 5
Page 13
STG4159 Package mechanical data
Figure 14. Package dimensions
Doc ID 12493 Rev 5 13/18
Page 14
Package mechanical data STG4159
Figure 15. Footprint recommendations
Figure 16. Marking
Dot, ST Logo
S1 = Marking
V = Manufacturing Location
yww = Datecode (y = year, ww = week)
Figure 17. Flip-chip 7 tape specification
14/18 Doc ID 12493 Rev 5
Page 15
STG4159 Package mechanical data
Figure 18. Flip-chip 7 reel information
Doc ID 12493 Rev 5 15/18
Page 16
Package mechanical data STG4159
Figure 19. Flip-chip 7 reel information
16/18 Doc ID 12493 Rev 5
Page 17
STG4159 Revision history
6 Revision history
Table 9. Revision history
Date Revision Changes
05-May-2006 1 First release
22-Nov-2006 2 Schematic Figure 1 on page 3 updated
17-Apr-2007 3 Typo in cover page description
06-May-2009 4 Device summary table updated, watermark removed from all pages.
01-Oct-2009 5
Modified: Figure 2, Figure 3, Section 4: Test circuits and Figure 14.
Updated: T
values in Tab le 4 , removed footnote in Ta bl e 5 .
stg
Doc ID 12493 Rev 5 17/18
Page 18
STG4159
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18/18 Doc ID 12493 Rev 5
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