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N-channel 900V - 0.21Ω - 28A ISOTOP
Zener-Protected SuperMESH™ MOSFET
General features
Type V
STE30NK90Z 900V <0.26Ω 28A 500W
■ Extremely high dv/dt capability
■ 100% avalanche tested
■ Gate charge minimized
DSS RDS(on)ID
Description
The SuperFREDMesh™ series is obtained
through an extreme optimization of ST’s well
established strip-based PowerMESH™ layout. In
addition to pushing on-resistance significantly
down, special care is taken to ensure a very good
dv/dt capability for the most demanding
applications. Such series complements ST full
range of high voltage MOSFETs including
revolutionary MDmesh™ products.
Pw
STE30NK90Z
iSOTOP
Internal schematic diagram
Applications
■ Switching application
Order codes
Part number Marking Package Packaging
STE30NK90Z E30NK90Z ISOTOP TUBE
July 2006 Rev 5 1/13
www.st.com
13
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Contents STE30NK90Z
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Protection features of gate-to-source zener diodes . . . . . . . . . . . . . . . . . . 5
2.2 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
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STE30NK90Z Electrical ratings
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
V
I
V
DGR
V
DM
P
I
I
DS
GS
D
D
(1)
tot
Drain-source voltage (VGS = 0) 900 V
Drain-gate voltage (RGS = 20 kΩ) 900 V
Gate- source voltage ± 30 V
Drain current (continuous) at TC = 25°C 28 A
Drain current (continuous) at TC = 100°C 18 A
Drain current (pulsed) 112 A
Total dissipation at TC = 25°C 500 W
Derating Factor 4.3 W/°C
V
ESD(G-S)
(2)
dv/dt
V
ISO
T
stg
T
j
1. Pulse width limited by safe operating area.
2. ISD ≤ 28A, di/dt ≤ 200A/µs, VDD ≤ V
Gate source ESD(HBM-C=100pF, R=1.5KW) 6.5 KV
Peak diode recovery voltage slope 4.5 V/ns
Insulation withstand voltage (AC-RMS) from all
four terminals to external heatsink
2500 V
Storage temperature
-65 to 150 °C
Max. operating junction temperature
,
(BR)DSS
Table 2. Thermal data
Rthj-case Thermal resistance junction-case max 0.23 °C/W
Rthj-amb Thermal resistance junction-ambient max 40 °C/W
Table 3. Avalanche characteristics
Symbol Parameter Max Value Unit
I
AR
E
Avalanche current, repetitive or not-repetitive
(pulse width limited by T
Max)
j
Single pulse avalanche energy
AS
(starting T
= 25 °C, ID = IAR, VDD = 35 V)
j
13 A
500 mJ
3/13
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Electrical characteristics STE30NK90Z
2 Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 4. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
Gate-body leakage
current (V
DS
= 0)
= 0)
ID = 1 mA, VGS = 0 900 V
V
= Max Rating
DS
VDS = Max Rating,
= 125 °C
T
C
10
100µAµA
VGS = ± 20V ±100 µA
Gate threshold voltage VDS = VGS, ID = 150 µA 3 3.75 4.5 V
Static drain-source on
resistance
V
= 10V, ID = 14 A 0.21 0.26 Ω
GS
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Forward
(1)
g
fs
transconductance
V
= 15 V, ID= 14 A 26 S
DS
C
C
oss
C
C
oss eq.
t
d(on)
t
t
d(off)
t
Q
Q
Q
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
2. C
oss eq.
increases from 0 to 80% V
Input capacitance
iss
output capacitance
reverse transfer
rss
capacitance
Equivalent output
(2)
capacitance
Turn-on delay time
rise time
r
turn-off delay time
fall time
f
Total gate charge
g
gate-source charge
gs
gate-drain charge
gd
is defined as a constant equivalent capacitance giving the same charging time as C
DSS
= 25V, f = 1 MHz,
V
DS
VGS = 0
= 0V,
V
GS
= 0V to 720 V
V
DS
= 450 V, ID = 13 A
V
DD
=4.7Ω VGS = 10 V
R
G
(see Figure 14)
VDD = 720 V, ID = 26 A,
= 10V
V
GS
(see Figure 15)
12000
852
166
377 pF
67
59
250
72
350
490 nC
51
190
when VDS
oss
pF
pF
pF
ns
ns
ns
ns
nC
nC
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STE30NK90Z Electrical characteristics
Table 6. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
t
Q
I
RRM
1. Pulse width limited by safe operating area%
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5
Source-drain current
Source-drain current
(1)
(pulsed)
(2)
Forward on voltage ISD = 28 A, VGS = 0 2 V
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
ISD = 26 A, di/dt = 100 A/µs
= 100 V, Tj = 25°C
V
DD
(see Figure 16)
ISD = 26 A, di/dt = 100 A/µs
VDD = 100 V, Tj = 150°C
(see Figure 16)
1
18.9
36.6
1.33
25.2
37.8
Table 7. Gate-source zener diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
BV
GSO
Gate-source breakdown
voltage
Igs=± 1mA (Open
Drain)
30 V
2.1 Protection features of gate-to-source zener diodes
28
112
A
A
µs
µC
A
µs
µC
A
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
5/13
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Electrical characteristics STE30NK90Z
2.2 Electrical characteristics (curves)
Figure 1. Safe operating area Figure 2. Thermal impedance
Figure 3. Output characterisics Figure 4. Transfer characteristics
Figure 5. Transconductance Figure 6. Static drain-source on resistance
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STE30NK90Z Electrical characteristics
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized B
vs temperature
VDSS
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Electrical characteristics STE30NK90Z
Figure 13. Avalanche energy vs starting Tj
8/13
Page 9
STE30NK90Z Test circuit
3 Test circuit
Figure 14. Switching times test circuit for
resistive load
Figure 16. Test circuit for inductive load
switching and diode recovery times
Figure 15. Gate charge test circuit
Figure 17. Unclamped Inductive load test
circuit
Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform
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Package mechanical data STE30NK90Z
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
10/13
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STE30NK90Z Package mechanical data
ISOTOP MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 11.8 12.2 0.466 0.480
B 8.9 9.1 0.350 0.358
C 1.95 2.05 0.076 0.080
D 0.75 0.85 0.029 0.033
E 12.6 12.8 0.496 0.503
F 25.15 25.5 0.990 1.003
G 31.5 31.7 1.240 1.248
H4 0.157
J 4.1 4.3 0.161 0.169
K 14.9 15.1 0.586 0.594
L 30.1 30.3 1.185 1.193
M 37.8 38.2 1.488 1.503
N4 0.157
O 7.8 8.2 0.307 0.322
O
mm inch
G
A
B
N
D
F
E
H
J
C
K
L
M
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Revision history STE30NK90Z
5 Revision history
Table 8. Revision history
Date Revision Changes
24-May-2005 1 First Release
10-Jun-2005 2 Inserted new row in Table 6.: Switching times
28-Sep-2005 3 Complete version
14-Oct-2005 4 Modified Figure 3, Figure 6
12-Jul-2006 5 New template, no content change
12/13
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STE30NK90Z
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