Datasheet std95nh02l_std95nh02l-1 Datasheet

N-channel 24V - 0.0039Ω - 80A - DPAK - IPAK

Ultra low gate charge STripFET™ Power MOSFET

Features

Type V

STD95NH02L 24V < 0.005Ω 80A

STD95NH02L-1 24V < 0.005Ω 80A

1. Value limited by wire bonding

■ Conduction losses reduced

■ Switching losses reduced

■ Low threshold device

DSS

Description

The device is based on the latest generation of
ST’s proprietary STripFET™ technology. An
innovative layout enables the device to also
exhibit extremely low gate charge for the most
demanding requirements in high-frequency DC­DC converters. It’s therefore ideal for high-density
converters in Telecom and Computer
applications.

R

DS(on)

I

D

(1)

(1)

STD95NH02L-1

STD95NH02L

3

2

1

IPAK

Figure 1. Internal schematic diagram

1

DPAK

3

Application

■ Switching applications

Table 1. Device summary

Order code

STD95NH02LT4 D95NH02L DPAK Tape & reel

STD95NH02L-1 D95NH02L IPAK Tube

August 2007 Rev 4 1/16

Marking Package Packaging

www.st.com

16

Contents STD95NH02L - STD95NH02L-1

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/16

STD95NH02L - STD95NH02L-1 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

(1)

V

spike

V

V

DGR

V

I

D

I

D

I

DM

P

TOT

EAS

T

T

1. Guaranteed when external Rg= 4.7Ω and Tf < Tfmax

2. Value limited by wire bonding

3. Pulse width limited by safe operating area

4. Starting Tj =25°C, Id = 40A, Vdd = 22V

DS

GS

(2)

(2)

stg

Drain-source voltage rating 30 V

Drain-source voltage (VGS = 0) 24 V

Drain-gate voltage (RGS = 20kΩ)24V

Gate-source voltage ± 20 V

Drain current (continuous) at TC = 25°C 80 A

Drain current (continuous) at TC = 100°C 68 A

(3)

Drain current (pulsed) 320 A

Total dissipation at TC = 25°C 100 W

Derating factor 0.67 W/°C

(4)

Single pulse avalanche energy 600 mJ

Operating junction temperature

j

Storage temperature

-55 to 175 °C

Table 3. Thermal data

Rthj-case Thermal resistance junction-case max 1.5 °C/W

Rthj-amb Thermal resistance junction-to ambient max 100 °C/W

T

J

Maximum lead temperature for soldering purpose 275 °C

3/16

Electrical characteristics STD95NH02L - STD95NH02L-1

2 Electrical characteristics

(T

=25°C unless otherwise specified)

CASE

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Drain-source
breakdown voltage

Zero gate voltage
drain current (VGS = 0)

Gate-body leakage
current (VDS = 0)

ID = 250µA, VGS =0 24 V

VDS = 20V
VDS = 20V, TC = 125°C

1

10

VGS = ± 20V ±100 nA

Gate threshold voltage VDS = VGS, ID = 250µA 1 V

Static drain-source on
resistance

= 10V, ID = 40A

V

GS

= 5V, ID = 40A

V

GS

0.0039

0.0055

0.005

0.009

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Forward

(1)

g

fs

C

C

C

t

d(on)

t

d(off)

Q
Q
Q

Q

oss

Q

gls

R

1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.

2. Q

oss.

3. Gate charge for synchronous operation

transconductance

Input capacitance

iss

Output capacitance

oss

Reverse transfer

rss

capacitance

Turn-on delay time

t

Rise time

r

Turn-off delay time

t

Fall time

f

Total gate charge

g

Gate-source charge

gs

Gate-drain charge

gd

(2)

Output charge V

Third-quadrant gate

(3)

charge

Gate Input Resistance

G

= C

* ∆ Vin, C

oss

oss

= Cgd + C

See Chapter 4: Appendix A

gd.

= 10V, ID= 10A 30 S

V

DS

= 15V, f = 1MHz,

V

DS

= 0

V

GS

= 12V, ID = 40A

V

DD

=4.7Ω VGS = 10V

R

G

(see Figure 14)

= 12V, ID = 80A,

V

DD

= 5V, RG=4.7Ω

V

GS

(see Figure 15)

=19V, V

V

DS

DS

< 0V, V

GS

GS

=0V 22.6 nC

= 5V 15 nC

2070

990

90

20

110

47
20

17

7.6

6.8

f=1MHz Gate DC
Bias =0 Test Signal

Level =20mV

1.8 Ω

Open Drain

µA
µA

Ω
Ω

pF
pF
pF

ns
ns
ns
ns

nC
nC
nC

4/16

STD95NH02L - STD95NH02L-1 Electrical characteristics

Table 6. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

SD

I

SDM

V

SD

t

Q

I

RRM

1. Pulse width limited by safe operating area.

2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

Source-drain current
Source-drain current

(1)

(pulsed)

(2)

Forward on voltage ISD = 40A, VGS = 0 1.3 V

Reverse recovery time

rr

Reverse recovery charge

rr

Reverse recovery current

ISD = 80A, di/dt = 100A/µs,
VDD = 20V, Tj = 150°C
(see Figure 16)

42

50.4

2.4

80

320

A
A

ns

nC

A

5/16

Electrical characteristics STD95NH02L - STD95NH02L-1

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance

Figure 4. Output characteristics Figure 5. Transfer characteristics

Figure 6. Transconductance Figure 7. Static drain-source on resistance

6/16

STD95NH02L - STD95NH02L-1 Electrical characteristics

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations

Figure 10. Normalized gate threshold voltage

vs temperature

Figure 12. Source-drain diode forward

characteristics

Figure 11. Normalized on resistance vs

temperature

Figure 13. Normalized BV

vs temperature

DSS

7/16

Test circuit STD95NH02L - STD95NH02L-1

3 Test circuit

Figure 14. Switching times test circuit for

resistive load

Figure 16. Test circuit for inductive load

switching and diode recovery times

Figure 15. Gate charge test circuit

Figure 17. Unclamped Inductive load test

circuit

Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform

8/16

STD95NH02L - STD95NH02L-1 Appendix A

V

4 Appendix A

Figure 20. Buck converter: power losses estimation

The power losses associated with the FETs in a synchronous buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.

● The low side (SW2) device requires:

● Very low R

● Small Qgls to reduce the gate charge losses

● Small Coss to reduce losses due to output capacitance

● Small Qrr to reduce losses on SW1 during its turn-on

● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source

● voltage to avoid the cross conduction phenomenon;

● The high side (SW1) device requires:

● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on

the gate

● Small Qg to have a faster commutation and to reduce gate charge losses

● Low R

DS(on)

to reduce conduction losses

DS(on)

to reduce the conduction losses.

Table 7. Power losses calculation

High side switching (SW1) Low side switch (SW2)

Pconduction

Pswitching Zero Voltage Switching

2

δ

*I *R

LDS(on)SW1

I

+

gd(SW1)gsth(SW1)in

L

*f*)Q(Q*

I

g

2
LDS(on)SW2

)1(*I *R

δ

−

9/16

Appendix A STD95NH02L - STD95NH02L-1

Table 7. Power losses calculation

High side switching (SW1) Low side switch (SW2)

Pdiode

Pgate(Q

Conductio

P

Qoss

Recovery

(1)

n

)

G

Not applicable

Not applicable

ggg(SW1)

oss(SW1)in

f*V*Q

f*Q*V

2

1. Dissipated by SW1 during turn-on

Table 8. Parameters meaning

Parameter Meaning

d Duty-cycle

Q

gsth

Q

gls

Pconduction On state losses

Pswitching On-off transition losses

Post threshold gate charge

Third quadrant gate charge

rr(SW2)in

oss(SW2)in

f*Q*V

deadtimeLf(SW2)

gggls(SW2)

f*t*I*V

f*V*Q

f*Q*V

2

Pdiode Conduction and reverse recovery diode losses

Pgate Gate drive losses

P

Qoss

Output capacitance losses

10/16

STD95NH02L - STD95NH02L-1 Package mechanical data

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com

11/16

Package mechanical data STD95NH02L - STD95NH02L-1

DPAK MECHANICAL DATA

DIM.

A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009

B 0.64 0.9 0.025 0.035

b4 5.2 5.4 0.204 0.212

C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244
D1 5.1 0.200

E 6.4 6.6 0.252 0.260
E1 4.7 0.185

e 2.28 0.090

e1 4.4 4.6 0.173 0.181

H 9.35 10.1 0.368 0.397

L 1 0.039

(L1) 2.8 0.110

L2 0.8 0.031
L4 0.6 1 0.023 0.039

R 0.2 0.008
V2 0° 8° 0° 8°

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

12/16

0068772-F

STD95NH02L - STD95NH02L-1 Package mechanical data

TO-251 (IPAK) MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A 2.2 2.4 0.086 0.094

A1 0.9 1.1 0.035 0.043

A3 0.7 1.3 0.027 0.051

B 0.64 0.9 0.025 0.031

B2 5.2 5.4 0.204 0.212

B3 0.85 0.033

B5 0.3 0.012

B6 0.95 0.037

C 0.45 0.6 0.017 0.023

C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

E 6.4 6.6 0.252 0.260

G 4.4 4.6 0.173 0.181

H 15.9 16.3 0.626 0.641

L 9 9.4 0.354 0.370

L1 0.8 1.2 0.031 0.047

L2 0.8 1 0.031 0.039

H

C

A

E

= =

C2

L2

B2

= =

D

B3

2

1 3

L1

B6

A1

A3

L

B

B5

G

= =

0068771-E

13/16

Packing mechanical data STD95NH02L - STD95NH02L-1

6 Packing mechanical data

DPAK FOOTPRINT

All dimensions are in millimeters

TAPE AND REEL SHIPMENT

REEL MECHANICAL DATA

DIM.

A 330 12.992

B 1.5 0.059

C 12.8 13.2 0.504 0.520

D 20.2 0.795

G 16.4 18.4 0.645 0.724

N 50 1.968

T 22.4 0.881

mm inch

MIN. MAX. MIN. MAX.

TAPE MECHANICAL DATA

DIM.

A0 6.8 7 0.267 0.275

B0 10.4 10.6 0.409 0.417

B1 12.1 0.476

D 1.5 1.6 0.059 0.063

D1 1.5 0.059

E 1.65 1.85 0.065 0.073

F 7.4 7.6 0.291 0.299

K0 2.55 2.75 0.100 0.108

P0 3.9 4.1 0.153 0.161

P1 7.9 8.1 0.311 0.319

P2 1.9 2.1 0.075 0.082

R 40 1.574

W 15.7 16.3 0.618 0.641

mm inch

MIN. MAX. MIN. MAX.

14/16

BASE QTY BULK QTY

2500 2500

STD95NH02L - STD95NH02L-1 Revision history

7 Revision history

Table 9. Revision history

Date Revision Changes

13-Sep-2004 1 First release

27-May-2005 2 Some values changed in Table 5: Dynamic.

09-Aug-2006 3 The document has been updated

02-Aug-2007 4 Error on cover page; added IPAK

15/16

STD95NH02L - STD95NH02L-1

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