The device is a NPN transistor manufactured
using planar Technology resulting in rugged high
performance devices.
Order codes
1
DPAK
Internal Schematic Diagram
Part NumberMarkingPackagePacking
STD724T4D724DPAKTape & reel
October 20051/10
www.st.com
Rev 2
10
Page 2
1 Electrical RatingsSTD724
1 Electrical Ratings
Table 1.Absolute Maximum Rating
SymbolParameterValueUnit
V
V
V
P
T
CBO
CEO
EBO
I
I
CM
I
I
BM
TOT
STG
T
Collector-Base Voltage (IE = 0)
Collector-Emitter Voltage (IB = 0)
Collector-Base Voltage (IC = 0)
Collector Current3A
C
Collector Peak Current (tP < 5ms)
Base Current1A
B
Base Peak Current (tP < 5ms)
Total di ssipation at Tc = 25°C
Storage Temperature
Max. Operating Junction Temperature
J
60V
30V
5V
6A
2A
15W
-65 to 150
150
Table 2.Thermal Data
SymbolParameterValueUnit
R
thj-amb
Thermal Resista nce Junction-Amb ____________________Max8.33°C/W
°C
2/10
Page 3
STD7242 Electrical Char acteristics
2 Electrical Characteristics
Table 3.Electrical Characteristics (T
= 25°C; unless otherwise specified)
CASE
SymbolParameterT est ConditionsMin.Typ.Max.Unit
I
CES
I
CEO
I
EBO
V
(BR)CBO
V
(BR)CEO
Note 1
V
(BR)EBO
V
CE(sat)
Note 1
V
BE(sat)
Note 1
h
Collector Cut-off Current
= 0)
(V
BE
Collector Cut-off Current
= 0)
(I
B
Emitter Cut-off Current
= 0)
(I
C
Collector-Base
Breakdown Voltage (I
Collector-Emit ter Breakdown
Voltage (I
= 0)
B
Collector-Emit ter Breakdown
Voltage (I
= 0)
C
Collector-Emitter Saturation
Voltage
Base-Emitter Saturation Voltage
DC Current Gain
FE
f
Transistor Frequency
T
= 0)
E
= 60V
V
CE
= 30V
V
CE
= 5V
V
EB
= 100μA
I
C
= 10 mA
I
C
= 100 μA
I
E
I
= 1 A IB = 50 mA
C
I
= 2 A IB = 100 mA
C
I
= 3 A IB = 150 mA
C
= 2 A IB = 100 mA
I
C
I
= 100 mA V
C
I
= 1 A V
C
= 3 A V
I
C
V
= 10 V Ic= 0.1 A
CE
CE
CE
CE
= 2 V
= 2 V
= 2 V
10μA
100μA
10μA
60V
30V
5V
0.4
0.7
1.1
1.2V
100
80
300
30
100MHz
1 Pulsed duration = 300 μs, duty cycle ≤1.5%.
V
V
V
3/10
Page 4
2 Electrical CharacteristicsSTD724
2.1 Electrical characteristics (curve)
Figure 1.DC Current GainFigur e 2.DC Current Gain
Figure 3.Collector-emitter saturation voltage Figure 4.Base-emitter satura tion voltage
Figure 5.Switching times on resistive loadFigure 6.Switching times resistive on load
4/10
Page 5
STD7242 Electrical Char acteristics
Figure 7.Reverse biased area
5/10
Page 6
3 Package Mechani cal DataSTD724
3 Package M echanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grante
y implic ation or otherwise unde r any patent or patent ri ghts of STMicroelectronics. Speci fications me ntioned in th i s publication are subje
o change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are n
uthoriz ed for use as critical component s i n l ife support devic es or systems wi th out express wr i tten approval of STMi croelectronics.
The ST logo is a registered trademark of STMi croelectronics.
All other nam es are the property of their re spective owners