This product utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology.
This is suitable for the most demanding DC-DC
converter application where high efficiency is to
be achieved.
Figure 5.TransconductanceFigure 6.Static drain-source on resistance
6/16
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Obsolete Product(s) - Obsolete Product(s)
STD70N03L - STD70N03L-1Electrical characteristics
Figure 7.Gate charge vs gate-source voltage Figure 8.Capacitance variations
Figure 9.Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized B
vs temperature
VDSS
7/16
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Obsolete Product(s) - Obsolete Product(s)
Test circuitSTD70N03L - STD70N03L-1
3 Test circuit
Figure 13. Switching times test circuit for
Figure 15. Test circuit for inductive load
resistive load
switching and diode recovery times
Figure 14. Gate charge test circuit
Figure 16. Unclamped inductive load test
circuit
Figure 17. Unclamped inductive waveformFigure 18. Switching time waveform
8/16
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Obsolete Product(s) - Obsolete Product(s)
STD70N03L - STD70N03L-1Power losses estimation
Appendix A Power losses estimation
Figure 19. Buck converter
The power losses associated with the FETs in a synchronous buck converter can
be estimated using the equations shown in the table below. The formulas give a
good approximation, for the sake of performance comparison, of how different
pairs of devices affect the converter efficiency. However a very important
parameter, the wotking temperature, is not considered. The real device behavior is
really dependent on how the heat generated inside the devices is removed to allow
for a safer working junction temperature.
The low side (SW2) device requires:
●Ver y low R
●Small Q
●Small C
●Small Q
●The C
gls
oss
rr
gd/Cgs
to reduce conduction losses
DS(on)
to reduce the gate charge losses
to reduce losses due to output capacitance
to reduce losses on SW1 during its turn-on
ratio lower than Vth/Vgg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon.
The high side (SW1) device requires:
●Small Rg and Lg to allow higher gate current peak and to limit the voltage
feedback on the gate
●Small Q
●Low R
to have a faster commutation and to reduce gate charge losses
PdiodeConduction and reverse recovery diode losses
PgateGate driver losses
P
Qoss
10/16
Post threshold gate charge
Third quadrant gate charge
Output capacitance losses
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Obsolete Product(s) - Obsolete Product(s)
STD70N03L - STD70N03L-1Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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