Datasheet std70n03l-1 Datasheet

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N-channel 30V - 0.0059Ω - 70A - DPAK / IPAK
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Obsolete Product(s) - Obsolete Product(s)
General features
Type V
STD70N03L 30V <0.0073Ω 70A
STD70N03L-1 30V <0.0073Ω 70A
DSS
R
DS(on)
STD70N03L
STD70N03L-1
STripFET™ III Power MOSFET
I
D
■ R
■ Conduction losses reduced
■ Switching losses reduced
■ Low threshold device
* Qg industry’s benchmark
Description
This product utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved.
Applications
■ Switching application
DPAK
3
1
IPAK
2
1
Internal schematic diagram
Order codes
Part number Marking Package Packaging
STD70N03L D70N03L DPAK Tape & reel
STD70N03L-1 D70N03L-1 IPAK Tube
June 2006 Rev 1 1/16
www.st.com
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Contents STD70N03L - STD70N03L-1
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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STD70N03L - STD70N03L-1 Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
V
DS
V
GS
I
D
I
D
I
DM
P
TOT
E
AS
T
T
stg
1. Pulse width limited by safe operating area
2. Starting Tj =25°C, Id = 30A, Vdd = 15V
Drain-source voltage (VGS = 0)
Gate-source voltage ± 20 V
Drain current (continuous) at TC = 25°C
Drain current (continuous) at TC = 100°C
(1)
Drain current (pulsed) 280 A
Total dissipation at TC = 25°C
Derating factor 0.47 W/°C
(2)
Single pulse avalanche energy 300 mJ
Operating junction temperature
j
Storage temperature
30 V
70 A
50 A
70 W
-55 to 175 °C
Table 2. Thermal resistance
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case Max 2.14 °C/W
Rthj-amb Thermal resistance junction-amb Max 100 °C/W
T
Maximum lead temperature for soldering purpose 275 °C
l
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Electrical characteristics STD70N03L - STD70N03L-1

2 Electrical characteristics

(T
=25°C unless otherwise specified)
CASE
Table 3. On/off states
Symbol Parameter Test condictions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown voltage
Zero gate voltage drain current (VGS = 0)
Gate body leakage current(V
DS
= 0)
Gate threshold voltage
Static drain-source on resistance
= 250µA, VGS= 0
I
D
V
= 20V,
DS
V
= 20V,Tc = 125°C
DS
= ±20V
V
GS
V
= VGS, ID = 250µA
DS
V
= 10V, ID= 35A
GS
V
= 5V, ID= 35A
GS
= 10V, ID= 35A @Tj=125°C
V
GS
= 5V, ID= 35A @Tj=125°C
V
GS
30 V
1
10
±100 nA
1V
0.0059
0.007
0.0091
0.0108
0.0073
0.013
0.0113
0.0201
Table 4. Dynamic
Symbol Parameter Test condictions Min. Typ. Max. Unit
µA µA
Ω Ω Ω Ω
Forward
(1)
g
fs
C
C
C
Q
Q
Q
Q
gls
R
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. Gate charge for synchronous operation: see Appendix A: Power losses estimation
transconductance
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
g
Total gate charge Gate-source charge
gs
Gate-drain charge
gd
Third-quadrant gate
(2)
charge
Gate input resistance
G
V
=10V, ID = 15A
DS
V
=25V, f=1MHz, VGS=0
DS
=15V, ID = 70A
V
DD
V
=5V
GS
(see Figure 7)
V
DS
<0V, V
GS
=10V
f=1MHz Gate DC Bias =0 Test signal level =20mV open drain
40 S
2200
380
49
15.7
21 nC
8.3
3.4
15 nC
1.5 Ω
pF pF pF
nC nC
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STD70N03L - STD70N03L-1 Electrical characteristics
Table 5. Switching times
Symbol Parameter Test condictions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off delay time Fall time
t
f
=15V, ID=35A,
V
DD
=4.7Ω, VGS=5V
R
G
(see Figure 13)
21 95 19 15
ns ns ns ns
Table 6. Source drain diode
Symbol Parameter Test condictions Min Typ. Max Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
Source-drain current 70 A
(1)
Source-drain current (pulsed) 280 A
(2)
Forward on voltage
rr
Reverse recovery time Reverse recovery charge
rr
Reverse recovery current
=35A, VGS=0
I
SD
= 70A,
I
SD
di/dt=100A/µs,
=20V, Tj=150°C
V
DD
(see Figure 18)
32 51
3.2
1.3 V
ns
nC
A
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Electrical characteristics STD70N03L - STD70N03L-1

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance
Figure 3. Output characterisics Figure 4. Transfer characteristics
Figure 5. Transconductance Figure 6. Static drain-source on resistance
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STD70N03L - STD70N03L-1 Electrical characteristics
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized B
vs temperature
VDSS
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Test circuit STD70N03L - STD70N03L-1

3 Test circuit

Figure 13. Switching times test circuit for
Figure 15. Test circuit for inductive load
resistive load
switching and diode recovery times
Figure 14. Gate charge test circuit
Figure 16. Unclamped inductive load test
circuit
Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform
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STD70N03L - STD70N03L-1 Power losses estimation
Appendix A Power losses estimation
Figure 19. Buck converter
The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the wotking temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature.
The low side (SW2) device requires:
● Ver y low R
● Small Q
● Small C
● Small Q
● The C
gls
oss
rr
gd/Cgs
to reduce conduction losses
DS(on)
to reduce the gate charge losses
to reduce losses due to output capacitance
to reduce losses on SW1 during its turn-on
ratio lower than Vth/Vgg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon.
The high side (SW1) device requires:
● Small Rg and Lg to allow higher gate current peak and to limit the voltage
feedback on the gate
● Small Q
● Low R
to have a faster commutation and to reduce gate charge losses
g
to reduce the conduction losses
DS(on)
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Power losses estimation STD70N03L - STD70N03L-1
High side switch (SW1) Low side switch (SW2)
P
conduction
P
switching
P
diode
P
gate(Qg)
R
DS on()IL
V
inQgsth SW1()Qgd SW1()
2
•δ•
+()• f
Recovery Not applicable
Conduction Not applicable
Q
• f•
gSW1()Vgg
2
R
I
L
----
••
I
g
Zero voltage switching
V
fSW2()ILtdeadtime
Q
• 1 δ–()•
DS on()IL
1
Q
• f•
V
rr SW2()
in
gls SW2()Vgg
• f•
f•••
P
Qoss
V
• f•
inQoss SW1()
------------------------------------------------- -
2
V
• f•
inQoss SW2()
------------------------------------------------- -
2
Parameter Meaning
d Duty-cycle
Q
gsth
Q
gls
Pconduction On state losses
Pswitching On-off transition losses
Pdiode Conduction and reverse recovery diode losses
Pgate Gate driver losses
P
Qoss
10/16
Post threshold gate charge
Third quadrant gate charge
Output capacitance losses
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STD70N03L - STD70N03L-1 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data STD70N03L - STD70N03L-1
TO-251 (IPAK) MECHANICAL DATA
DIM.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.3 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039
MIN. TYP. MAX. MIN. TYP. MAX.
A
mm inch
H
C
B5
A3
G
= =
E
= =
C2
L2
B2
= =
D
B3
2
1 3
L1
B6
A1
L
B
0068771-E
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STD70N03L - STD70N03L-1 Package mechanical data
DPAK MECHANICAL DATA
DIM.
A 2.2 2.4 0.086 0.094 A1 0.9 1 .1 0.035 0.043 A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035 b4 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
D1 5.1 0.200
E 6.4 6.6 0.252 0.260 E1 4.7 0.185
e 2.28 0.090 e1 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L1 0.039
(L1) 2.8 0.110
L2 0.8 0.031 L4 0.6 1 0.023 0.039
R 0.2 0.008 V2 0° 8° 0° 8°
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
0068772-F
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Packaging mechanical data STD70N03L - STD70N03L-1

5 Packaging mechanical data

DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM.
A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0.795
G 16.4 18.4 0.645 0.724
N 50 1.968
T 22.4 0.881
mm inch
MIN. MAX. MIN. MAX.
TAPE MECHANICAL DATA
DIM.
A0 6.8 7 0.267 0.275
B0 10.4 10.6 0.409 0.417
B1 12.1 0.476
D 1.5 1.6 0.059 0.063
D1 1.5 0.059
E 1.65 1.85 0.065 0.073
F 7.4 7.6 0.291 0.299
K0 2.55 2.75 0.100 0.108
P0 3.9 4.1 0.153 0.161
P1 7.9 8.1 0.311 0.319
P2 1.9 2.1 0.075 0.082
R 40 1.574
W 15.7 16.3 0.618 0.641
mm inch
MIN. MAX. MIN. MAX.
BASE QTY BULK QTY
2500 2500
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STD70N03L - STD70N03L-1 Revision history

6 Revision history

Table 7. Revision history
Date Revision Changes
29-Jun-2006 1 First Release
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STD70N03L - STD70N03L-1
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